Stacked Semiconductor Device Via Coupling
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Solution Overview
Problem
In multilayer semiconductor devices, the parasitic capacitance in the signal pathway between stacked semiconductor chips limits the drive capability and operation speed, necessitating a reduction in this capacitance to enhance performance aspects such as power consumption and speed.
Innovation Solution
The semiconductor device employs a shift circular coupling method for through-silicon vias, where the first group of vias is coupled in a specific circular pattern and the second group in another, ensuring that n and m have only one common divisor, allowing for efficient signal transmission and activation of stacked chips using selection signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If through-silicon vias are used to couple stacked semiconductor chips, then the chips can be interconnected in three dimensions enabling higher integration, but parasitic capacitance in the signal pathway increases which limits drive capability and operation speed
Solution Approach 1:
The through-silicon vias are segmented into multiple groups (first group with n vias, second group with m vias) rather than using a single uniform set of vias. This segmentation allows independent optimization of signal pathways and reduces parasitic capacitance effects by distributing the electrical load across multiple smaller via groups.
Solution Approach 2:
The patent employs asymmetric coupling patterns where the first group of via n and second group of via m have different quantities and coupling configurations. By setting n and m to have only one common divisor, the invention creates an asymmetric via arrangement that optimizes signal transmission characteristics and minimizes parasitic capacitance interference.
2Productivity
If through-silicon vias are used to couple stacked semiconductor chips, then the chips can be interconnected in three dimensions enabling higher integration, but parasitic capacitance in the signal pathway increases which raises power consumption
Solution Approach 1:
The through-silicon vias are segmented into multiple groups (first group with n vias, second group with m vias) rather than using a single uniform set of vias. This segmentation allows independent optimization of signal pathways and reduces parasitic capacitance effects by distributing the electrical load across multiple smaller via groups.
Solution Approach 2:
The invention changes the parameters of the via coupling system by specifying that n and m have only one common divisor, creating an optimized via arrangement that reduces parasitic capacitance and consequently lowers power consumption for signal transmission.
3Speed
If multiple through-silicon vias are used for chip coupling, then signal transmission capability is improved, but the complexity of via coupling and chip selection increases
Solution Approach 1:
The through-silicon vias are segmented into multiple groups (first group with n vias, second group with m vias) rather than using a single uniform set of vias. This segmentation allows independent optimization of signal pathways and reduces parasitic capacitance effects by distributing the electrical load across multiple smaller via groups.
Solution Approach 2:
The invention changes the parameters of the via coupling system by specifying that n and m have only one common divisor, creating an optimized via arrangement that reduces parasitic capacitance and consequently lowers power consumption for signal transmission.
Data Source
AI summary
A semiconductor device which reduces power consumption. In the semiconductor device, semiconductor chips are stacked over a base chip. The stacked chips include n through-silicon vias as a first group and m through-silicon vias as a second group. In each of the first and second groups, the through-silicon vias are coupled by a shift circular method, in which the 1st to (n−1)th ((m−1)th) through-silicon vias of a lower chip are coupled with the 2nd to n-th (m-th) through-silicon vias of an upper chip respectively and the n-th (m-th) through-silicon via of the lower chip is coupled with the 1st through-silicon via of the upper chip. n and m have only one common divisor. Activation of the stacked semiconductor chips is controlled by combination of a first selection signal transmitted through through-silicon vias of the first group and a second selection signal transmitted through through-silicon vias of the second group.