Stacked Semiconductor Device Via Formation
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Solution Overview
Problem
The manufacturing of surface mount semiconductor devices with vertically stacked electronic components faces challenges in forming reliable and cost-effective vertical vias, which are crucial for increased circuit complexity and reduced package size, while maintaining productivity and avoiding additional equipment or processes.
Innovation Solution
The method involves creating a structure with conductive frame members and apertures, embedding semiconductor dies, and forming redistribution layers to connect internal and external contacts, with exposed via members at the back face for vertical component connection, using techniques like grinding and laser ablation to reduce thickness and enhance via exposure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If vertically stacked electronic components are used to increase circuit complexity, then the active face area can be reduced, but the manufacturing complexity and reliability of via formation increase
Solution Approach 1:
Conductive via members are pre-formed on the rear surface of the substrate before die attachment. This preliminary formation of vias eliminates the need for complex post-assembly via creation processes, allowing vertical stacking while maintaining manufacturing simplicity.
Solution Approach 2:
Instead of forming vias through the substrate from the front (active face) after die attachment, the patent inverts the approach by forming vias from the rear surface of the substrate. This reversal simplifies the via formation process and enables easier access for connecting vertical components.
2Reliability
If conventional via formation techniques are used, then vertical connections can be established, but productivity decreases and additional equipment or processes are required
Solution Approach 1:
The substrate's rear surface is used to expose via members for direct connection to vertical components. This self-service approach eliminates the need for additional via formation equipment or processes, as the via members are inherently provided by the substrate structure itself, thereby improving productivity while maintaining reliability.
3Ease of operation
If the substrate thickness is reduced to expose via members, then vertical component connection is enabled, but manufacturing precision requirements increase
Solution Approach 1:
The conductive via members are pre-formed extending through or through-holes in the substrate before thickness reduction. This preliminary positioning ensures that even after thickness reduction by grinding or laser ablation, the via members remain properly exposed and aligned, reducing the precision burden on the thickness reduction step.
Solution Approach 2:
The via members extend in the vertical dimension through the substrate, providing a third dimension for connection. This dimensional approach allows via exposure through simple thickness reduction rather than requiring precise lateral positioning, thereby easing manufacturing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher productivity, reliability, and lower costs by allowing precise positioning and finer feature sizes, improving the connection of vertically stacked components without necessitating specific equipment or additional processes, thus addressing manufacturing issues related to via formation.
Implementation Method 1
using techniques like grinding and laser ablation to reduce thickness and enhance via exposure
Data Source
AI summary
A method of assembling semiconductor devices includes providing a structure that includes an array of conductive frame members beside an array of apertures and an array of conductive vias that are exposed at a first face and extend towards a second face. An array of semiconductor dies is positioned in the array of apertures with their active faces positioned in the first face of the structure. The assembly is encapsulated from the second face of the structure and a redistribution layer is formed on the first face of the structure and the active faces of the die. Material is removed from the back face of the encapsulated array to expose the vias at the back face for connection through a further redistribution layer formed on the back face to electronic components stacked vertically on the further redistribution layer.