Stacked Semiconductor Via Layout for Signal and Power Integrity
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Solution Overview
Problem
Contemporary semiconductor packages face challenges in reducing power loss due to electrical resistance and ensuring improved signal and power integrity, particularly in stacked semiconductor chips connected using through vias, where existing methods fail to optimize the size and structure of these vias for efficient signal and power transmission.
Innovation Solution
The semiconductor chip design incorporates a first through via with a smaller height and a second through via with a larger height, where the first via communicates non-power signals and the second via communicates power signals, utilizing insulating layers to minimize electrical resistance and optimize signal and power integrity, and the semiconductor package includes these chips stacked with specific wiring layers and insulating structures to enhance integration and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If through vias are used to connect stacked semiconductor chips, then operating speed is improved and power consumption is reduced, but electrical resistance causes power loss and degrades signal integrity
Solution Approach 1:
The patent applies local quality by differentiating the heights of through vias based on their specific functions: first through vias (shorter) for non-power signals and second through vias (taller) for power signals. This localized optimization reduces electrical resistance for power transmission while maintaining signal integrity, directly addressing the power loss issue without compromising operating speed.
Solution Approach 2:
The patent changes the physical parameter of through via height to optimize performance. By varying the height parameter according to the signal type (power vs. non-power), the invention minimizes electrical resistance effects and power loss while preserving the speed improvements gained from through via technology.
2Use of energy by moving object
If through vias are used to connect stacked semiconductor chips, then power consumption is reduced, but electrical resistance degrades signal and power integrity
Solution Approach 1:
The patent implements local quality by creating distinct through via structures optimized for different signal types. Second through vias with greater height are specifically designed for power signal transmission to minimize resistance and maintain power integrity, while first through vias handle non-power signals. This localized optimization preserves signal and power integrity while maintaining reduced power consumption.
Solution Approach 2:
The patent segments the through via system into two types based on function: first through vias for non-power signals and second through vias for power signals. This segmentation allows each via type to be optimized independently, ensuring that power signals maintain integrity through taller vias with lower resistance while non-power signals use shorter vias, thereby preserving overall system reliability.
3Loss of energy
If smaller through vias are used to reduce power loss, then electrical resistance is minimized, but the ability to transmit both power and non-power signals efficiently is compromised
Solution Approach 1:
The patent segments the via system into first through vias (shorter) for non-power signals and second through vias (taller) for power signals. This segmentation enables each via type to be optimized for its specific function: second through vias have greater height to minimize resistance for power transmission, while first through vias are optimized for signal transmission. The system thereby achieves both reduced power loss and maintained versatility in signal transmission.
Solution Approach 2:
The patent applies local quality by assigning different height characteristics to through vias based on their functional requirements. Power signal through vias (second through vias) are taller to reduce resistance and power loss, while non-power signal through vias (first through vias) are shorter. This localized differentiation preserves the system's ability to efficiently transmit both power and non-power signals while minimizing overall power loss.
Data Source
AI summary
A semiconductor chip may include; a device layer including transistors on a substrate, a wiring layer on the device layer, a first through via passing through the device layer and the substrate, and a second through via passing through the wiring layer, the device layer and the substrate, wherein a first height of the first through via is less than a second height of the second through via.