Stacked Semiconductor Package Via Repair Pads
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Solution Overview
Problem
The manufacturing yield of stacked semiconductor packages using through-silicon vias is compromised due to connection failures between the vias, which can lead to incomplete signal transfer and render the entire package unusable.
Innovation Solution
A stacked semiconductor package design that includes through-silicon vias, repair pads, and wiring lines connecting these vias, with additional interconnections and conductive members to ensure electrical connectivity, even in case of connection failures, and a molding part that seals and supports the package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If through-silicon vias are used to connect stacked semiconductor chips, then operation speed is improved and miniaturization is achieved, but connection failures between vias occur leading to decreased manufacturing yield
Solution Approach 1:
The patent applies preliminary action by forming repair pads and wiring lines during the initial chip fabrication process, before stacking occurs. These repair structures are pre-positioned on each chip's side surface, enabling future connection repairs without requiring chip redesign or complex post-assembly modifications. This proactive preparation directly addresses the reliability issue while maintaining the speed benefits of through-silicon vias.
Solution Approach 2:
The patent introduces repair pads as intermediary elements that facilitate alternative signal paths. When through-silicon via connections fail, the repair pads serve as mediator points that allow signal rerouting through wiring lines to adjacent functional vias, maintaining system operation. This intermediary structure resolves the contradiction by providing a backup mechanism that preserves both the miniaturization benefits and improves manufacturing yield.
2Volume of moving object
If through-silicon vias are used for electrical connections in stacked packages, then miniaturization is achieved, but connection failures render the entire package unusable
Solution Approach 1:
The patent applies segmentation by dividing the electrical connection system into multiple independent pathways. Instead of relying on a single direct via connection, the design segments the signal path to include alternative routes through repair pads and wiring lines. This segmentation allows partial functionality to be maintained even when some via connections fail, preserving package functionality while achieving miniaturization.
Solution Approach 2:
The patent utilizes parameter changes by modifying the electrical connection architecture from a single-path to a multi-path system. The repair pads and wiring lines create parallel conduction paths, changing the electrical parameters of the connection system to include redundancy. This parameter change enables the package to maintain functionality despite connection failures, while the overall miniaturized structure is preserved.
Data Source
AI summary
A stacked semiconductor package includes a plurality of semiconductor chips each including a substrate having one surface, the other surface which faces away from the one surface and side surfaces which connect the one surface and the other surface, through-silicon vias which pass through the one surface and the other surface of the substrate, repair pads which are exposed on the side surfaces of the substrate, and wiring lines which electrically connect the through-silicon vias with the repair pads, the plurality of semiconductor chips being stacked such that through-silicon vias of the semiconductor chips are connected with one another; and interconnections electrically connecting the repair pads of the semiconductor chips.