Stacked Semiconductor Device Via Segmentation
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Solution Overview
Problem
Existing semiconductor devices with stacked DRAM chips face issues of increased power consumption and yield deterioration when attempting to enhance data transfer speed, due to parasitic resistance and capacitance effects, leading to unstable operation and manufacturing challenges.
Innovation Solution
The solution involves a semiconductor device configuration where multiple chip dies are stacked with through-silicon vias (TSVs) and switches, allowing data signals to be transmitted through a reduced number of vias, reducing the data transfer rate per via and enabling stable operation at lower power consumption, and utilizing system control signals to manage chip groups and optimize output buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer speed is increased to enhance performance, then productivity is improved, but power consumption increases and yield deteriorates due to parasitic resistance and capacitance effects
Solution Approach 1:
The patent segments the data transfer function by introducing intermediate buffer circuits at each via level. Instead of direct high-speed transmission through multiple stacked chips, data is broken into segments that are buffered and retransmitted at each intermediate stage, reducing the speed requirement for individual via connections while maintaining overall high throughput.
Solution Approach 2:
The patent introduces intermediate buffer circuits as mediators between stacked chip layers. These buffers act as signal conditioning stations that reduce the impact of parasitic effects by regenerating and retiming signals, enabling stable high-speed operation without directly transmitting high-frequency signals through the entire stack.
2Productivity
If data transfer speed is increased to enhance performance, then productivity is improved, but manufacturing precision deteriorates due to difficulties in fabricating high-frequency operating chips
Solution Approach 1:
The patent divides the high-frequency transmission requirement into multiple lower-frequency stages. Each chip layer operates at a manageable frequency that is easier to fabricate and test, while the cumulative effect across multiple layers achieves the desired overall data transfer speed, reducing manufacturing complexity.
Solution Approach 2:
The patent implements preliminary signal conditioning and buffering at each via level before signals propagate to the next chip layer. This preliminary action of signal regeneration and timing adjustment simplifies the fabrication requirements for each individual chip by reducing the frequency and performance demands on each manufacturing stage.
3Productivity
If data transfer speed is increased to enhance performance, then productivity is improved, but reliability decreases due to unstable operation during communication with memory controller
Solution Approach 1:
The patent introduces intermediate buffer circuits as mediators that isolate and stabilize signals between chip layers and the memory controller. These buffers condition signals to eliminate timing violations and reduce susceptibility to noise and interference, ensuring reliable operation even at high data transfer speeds.
Solution Approach 2:
The patent performs preliminary signal conditioning, timing adjustment, and voltage level translation at each intermediate buffer stage before signals reach the next chip or the memory controller. This preliminary preparation of signals prevents instability and ensures reliable communication throughout the stacked memory system.
Data Source
AI summary
A method of testing a semiconductor device includes providing a first wafer that includes a first surface, a second surface that is allocated at an opposite side of the first surface, a first electrode penetrating the first wafer from the first surface to the second surface, and a pad formed on the first surface and coupled electrically with the first electrode, providing a second wafer that includes a second electrode penetrating the second wafer, stacking the first wafer onto the second wafer to connect the first electrode with the second electrode such that the second surface of the first wafer faces the second wafer, probing a needle to the pad, and supplying, in such a state that the first wafer is stacked on the second wafer, a test signal to the first electrode to input the test signal into the second wafer via the first electrode and the second electrode.