Stacked Semiconductor Package With Bridge Die Voltage Regulation
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Solution Overview
Problem
The increasing demand for multifunctional and high-volume data processing in electronic products poses a challenge due to limitations in semiconductor integration technology, making it difficult to satisfy functional requirements with a single semiconductor chip, necessitating the development of semiconductor packages with stacked semiconductor chips and efficient voltage regulation.
Innovation Solution
A semiconductor package design that includes a stack of semiconductor chips in the vertical direction, a bridge die stack with through electrodes and a connection electrode, a redistribution layer, and a voltage regulator with components like a switch, diode, capacitor, and inductor, which allows for efficient voltage adjustment and power supply to a logic chip, improving heat dissipation and power delivery while maintaining a compact package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor chips are stacked vertically to increase integration, then functional requirements and data processing capacity are improved, but voltage regulation and power supply complexity increase
Solution Approach 1:
The patent transitions from planar voltage regulation to three-dimensional vertical stacking, where voltage regulators are integrated within the stacked chip structure. Through-electrodes and power delivery networks extend vertically across multiple chip layers, enabling power supply in the vertical dimension rather than only horizontal plane, thus supporting high-density integration while managing voltage regulation complexity.
Solution Approach 2:
The patent implements nested voltage regulation by placing voltage regulator components within the internal structure of the stacked chip package. Power delivery networks are embedded within the interconnect structures between chips, and voltage regulators are integrated into the substrate or intermediate layers, creating a nested architecture where power management is embedded within the computational structure rather than added as external complexity.
2Use of energy by moving object
If voltage regulators are integrated within the stacked chip structure, then power supply efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary alignment features such as alignment marks, positioning protrusions, and pre-defined through-electrode locations that are established during chip fabrication before stacking. These pre-configured alignment mechanisms enable precise registration of multiple chips and integrated voltage regulator components during the assembly process, reducing the actual manufacturing precision demands during final assembly.
Solution Approach 2:
The patent introduces intermediary structures such as substrate boards, interconnect layers, and alignment fixtures that mediate between the chips and voltage regulator components. These intermediary elements provide mechanical support, electrical connection, and alignment reference, thereby reducing the direct precision requirements between stacked chips and integrated power management components.
3Power
If through-electrodes are used to connect bridge dies vertically, then power delivery capability is improved, but device complexity increases
Solution Approach 1:
The patent designs through-electrodes to serve multiple functions simultaneously: they provide mechanical support between stacked chips, establish electrical connections for signal transmission, and deliver power across multiple voltage levels. This multi-functionality reduces the need for separate dedicated power interconnect structures, thereby managing complexity while enhancing power delivery capability.
Solution Approach 2:
The patent merges power delivery paths with signal interconnect structures by integrating power and ground through-electrodes alongside data and control through-electrodes in the same vertical interconnect channels. This consolidation of power and signal pathways into unified interconnect structures reduces overall device complexity compared to having separate dedicated power delivery networks.
Data Source
AI summary
A semiconductor package includes: a first semiconductor chip stack including a plurality of first semiconductor chips which are stacked in a vertical direction; a bridge die stack disposed to be spaced apart from the first semiconductor chip stack in a horizontal direction and including a plurality of bridge dies which are stacked in the vertical direction, wherein the bridge dies include through electrodes, respectively, and the through electrodes aligned in the vertical direction are connected to each other through a connection electrode between the bridge dies; a redistribution layer disposed over the first semiconductor chip stack and the bridge die stack; a second semiconductor chip disposed over the redistribution layer and configured to receive a voltage through the through electrodes aligned in the vertical direction, the connection electrode, and the redistribution layer; and a voltage regulator configured to adjust the voltage.