Stacked Semiconductor Device Wafer-Level Bonding Parasitics
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Solution Overview
Problem
Traditional passive device/CMOS integration requires large passive devices for high capacitances or inductances, leading to longer electrical paths, increased parasitics, difficulty in shrinking system size, and higher fabrication costs due to precision and assembly challenges.
Innovation Solution
A wafer-level method for fabricating a stacked semiconductor device that aligns and bonds substrates with passive and CMOS devices using conductive wafer bonding or through-substrate vias (TSVs) to reduce electrical parasitics and assembly effort, allowing for more compact integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large passive devices are used to achieve high capacitances or inductances, then the required electrical capacitance or inductance is achieved, but the chip size increases and electrical path length increases
Solution Approach 1:
The patent transitions from planar integration to three-dimensional stacked integration. Passive devices and CMOS devices are fabricated on separate substrates and then vertically stacked and bonded together. This vertical arrangement in the third dimension allows high capacitance/inductance passive devices to be achieved without increasing the lateral chip footprint, as the large passive device structures extend in the vertical direction rather than the horizontal plane.
Solution Approach 2:
The patent merges the fabrication of passive devices and CMOS devices into a single integrated stack. By bonding substrates containing both passive and CMOS devices together with precise alignment, the system achieves compact integration where both device types coexist in a unified three-dimensional structure, eliminating the need for separate large-area passive device regions.
2Reliability
If large passive devices are used to achieve high capacitances or inductances, then the required electrical capacitance or inductance is achieved, but the electrical path length increases causing increased parasitics
Solution Approach 1:
By moving to vertical stacking in the third dimension, the electrical connections between passive and CMOS devices are shortened. The vertical bond pads and interconnect structures provide direct electrical pathways through the substrate thickness rather than requiring long lateral traces across the chip surface, thereby reducing resistive and capacitive parasitics associated with long electrical paths.
3Reliability
If individual wire bonding is used to connect passive devices to CMOS chip, then electrical connection is achieved, but assembly precision requirements increase and fabrication costs increase
Solution Approach 1:
The patent combines passive device substrates and CMOS device substrates into a single bonded structure during the fabrication process. By integrating both device types on separate substrates that are subsequently bonded together with precise alignment, the system eliminates the need for separate post-fabrication wire bonding operations. This merged approach reduces assembly steps, lowers fabrication costs, and maintains high connection reliability through direct substrate bonding interfaces.
Solution Approach 2:
The patent performs substrate alignment and bonding operations at the wafer level before dicing into individual devices. By pre-aligning and bonding entire substrates containing multiple devices while they are still in wafer form, the process achieves high precision through wafer-level alignment techniques, then separates the bonded substrates into individual stacked devices. This preliminary action at the wafer level is more efficient and precise than individual device assembly.
4Reliability
If individual wire bonding is used to connect passive devices to CMOS chip, then electrical connection is achieved, but assembly time and effort increase
Solution Approach 1:
The patent performs substrate alignment and bonding operations at the wafer level before dicing into individual devices. By pre-aligning and bonding entire substrates containing multiple devices while they are still in wafer form, the process achieves high precision through wafer-level alignment techniques, then separates the bonded substrates into individual stacked devices. This preliminary action at the wafer level is more efficient and precise than individual device assembly.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes electrical parasitics, stabilizes system performance, and reduces assembly costs by eliminating the need for external wire bonding and improving precision in integrating passive and CMOS devices.
Implementation Method 1
aligning and bonding substrates with passive and CMOS devices using conductive wafer bonding
Implementation Method 2
providing a through-substrate-via (TSV) through the first substrate to interconnect the first and second electrical devices
Data Source
AI summary
The present disclosure provides one embodiment of a stacked semiconductor device. The stacked semiconductor device includes a first substrate; a first bond pad over the first substrate; a second substrate including a second electrical device fabricated thereon; a second bond pad over the second electrical device over the second substrate, the second bond pad electrically connecting to the second electrical device; a second insulation layer over the second bond pad having a top surface, the second insulation layer being bonded toward the first bond pad of the first substrate; and a through-substrate-via (“TSV”) extending from a surface opposite to the first bond pad through the first substrate and through the top surface of the second insulation layer to the second bond pad.