Stacked Semiconductor Wafer Assembly Via Alignment
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Solution Overview
Problem
Conventional 3-dimensional semiconductor devices face issues with poor reliability and low yield due to stress concentration and incomplete etching caused by through vias, which restrict wafer thickness and aspect ratio, leading to performance deterioration.
Innovation Solution
The method involves stacking wafer assemblies with a glass substrate interconnect wafer and a semiconductor active wafer, using direct wafer bonding to align conductive through vias, allowing for reduced active wafer thickness and standardized interconnect wafers to support and protect the active parts, facilitating easier through via formation and increasing mechanical strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the wafer thickness is reduced to enable through via formation, then the aspect ratio of through hole decreases making etching easier, but the mechanical strength of wafer deteriorates causing breakage during transfer
Solution Approach 1:
The invention divides the wafer structure into two separate functional parts: an active wafer containing the semiconductor devices and an interconnect wafer containing the through vias. This segmentation allows each part to be optimized independently - the active wafer can maintain sufficient thickness for mechanical strength while the interconnect wafer provides the through via interconnections, thus resolving the contradiction between thin wafer requirement for via formation and thick wafer requirement for mechanical strength.
Solution Approach 2:
The invention introduces an interconnect wafer as an intermediary component between active wafers. This interconnect wafer serves as a mediator that provides the through via interconnections without requiring the active wafer to be thinned, thereby enabling complete etching while maintaining the mechanical strength of the active devices.
2Strength
If the wafer thickness is increased to maintain mechanical strength, then the wafer can withstand transfer processes, but the aspect ratio of through hole increases making etching incomplete leading to open-circuit failure
Solution Approach 1:
By segmenting the wafer into active and interconnect parts, the invention allows the interconnect wafer to be specifically designed with optimal thickness for through via formation, ensuring complete etching and reliable interconnections, while the active wafer maintains sufficient thickness for mechanical strength.
Solution Approach 2:
The invention applies different quality requirements to different parts: the interconnect wafer is designed with thickness optimized for via etching (lower mechanical strength requirement), while the active wafer is designed with thickness optimized for mechanical strength and device performance. This local differentiation resolves the contradiction between thick wafer for strength and thin wafer for complete etching.
3Ease of manufacture
If through vias are formed directly on active wafers, then interconnect is achieved, but stress concentration occurs near through vias causing performance deterioration
Solution Approach 1:
The invention segments the through via formation process from the active device structure by placing through vias in a separate interconnect wafer. This segmentation eliminates stress concentration near through vias in the active devices, as the vias are now in a dedicated interconnect structure designed to handle the mechanical and electrical interconnection functions without affecting active device performance.
4Ease of manufacture
If conventional through via formation is used, then wafer interconnection is achieved, but design limitation is imposed on stack-type semiconductor device
Solution Approach 1:
By separating active wafers from interconnect wafers, the invention provides independent design freedom for each type. Active wafers can be designed purely for device functionality without being constrained by via formation requirements, while interconnect wafers can be designed purely for interconnection functionality. This segmentation removes design limitations and enhances adaptability for stack-type semiconductor devices.
Solution Approach 2:
The interconnect wafer serves as a universal component that can be designed once and reused across multiple active wafers in a stack configuration. This multi-functionality approach standardizes the interconnection structure while allowing flexible design of active devices, thereby enhancing design versatility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances manufacturing yield and reliability by supporting the active wafer during processing, reduces manufacturing costs, and allows for easier formation of conductive through vias, addressing the limitations of conventional through via formation methods.
Implementation Method 1
bonding the first wafer assembly and the second wafer assembly together by a direct wafer bonding process so that the conductive through vias in the active part of the first wafer assembly are electrically coupled with the conductive through vias in the interconnect part of the second wafer assembly
Data Source
AI summary
A stack-type semiconductor device includes a semiconductor substrate; and a plurality of wafer assemblies arranged in various levels on the semiconductor substrate, in which the wafer assembly in each level includes an active part and an interconnect part, and the active part and the interconnect part each have conductive through vias, wherein the conductive through vias in the active part are aligned with the conductive through vias in the interconnect part in a vertical direction, so that the active part in each level is electrically coupled with the active part in the previous level and/or the active part in the next level by the conductive through vias. Such a stack-type semiconductor device and the related methods can be applied in a process after the FEOL or in a semiconductor chip packaging process and provide a 3-dimensional semiconductor device of high integration and high reliability.