Stacked Semiconductor Package Warpage Prevention

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Solution Overview

Problem

The manufacturing yield of stacked semiconductor packages is compromised due to warpage and cracking issues caused by the back-grinding process, which affects the stacking and electrical connectivity of semiconductor chips.

Innovation Solution

A stacked semiconductor package structure that includes first and second semiconductor chips with through electrodes, a molding part using epoxy molding compound, conductive connection members, and an adhesive member to prevent warpage and cracking, along with a method for manufacturing that involves forming and exposing through electrodes, stacking, and individualizing the chips while using conductive and non-conductive materials for secure connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the back-grinding process is used to thin semiconductor chips, then miniaturization is achieved, but warpage and cracking occur reducing manufacturing yield

Engineering Contradiction:

Improvechip thicknessVSAvoidmanufacturing yield

Core Design Contradiction:

Volume of moving objectVSReliability

Solution Approach 1:

A molding part is formed on the front surface of the semiconductor chip before the back-grinding process. This molding part serves as a protective structure that prevents warpage and cracking during the subsequent back-grinding operation, allowing the chip to be thinned without compromising manufacturing yield

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The molding part acts as a cushioning structure formed beforehand on the front surface of the chip. This cushioning structure absorbs and distributes the mechanical stress generated during back-grinding, preventing the chip substrate from warping or cracking while enabling miniaturization

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

2Reliability

If through electrodes are formed to connect upper and lower chips, then electrical connectivity and high operation speed are achieved, but the stacking process becomes complex

Engineering Contradiction:

Improveelectrical connectivityVSAvoidstacking process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The electrical connection structure is segmented into through electrodes formed within the chip substrate and bonding pads on the surface. This segmentation allows the through electrodes to be formed independently during chip fabrication, and the bonding pads to be used for stacking, simplifying the overall stacking process while maintaining reliable electrical connectivity

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS9252139B2Stacked semiconductor package and method for manufacturing the same

Publication Date: 2016.02.02 MIMIRIP LLC

AI summary

A stacked semiconductor package includes a first semiconductor chip having a first surface and a second surface which faces away from the first surface and including first bonding pads which are formed on the first surface and first through electrodes which pass through the first surface and the second surface; a second semiconductor chip stacked over the second surface of the first semiconductor chip, and including second bonding pads which are formed on a third surface facing the first semiconductor chip and second through electrodes which pass through the third surface and a fourth surface facing away from the third surface and are electrically connected with the first through electrodes; and a molding part formed to substantially cover the stacked first and second semiconductor chips and having openings which expose one end of the first through electrodes disposed on the first surface of the first semiconductor chip.