Stacked Semiconductor Device Warping Prevention
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Solution Overview
Problem
Conventional multilayer semiconductor devices experience defective connections due to warping caused by thermal expansion coefficient differences and heat generation during the reflow process, leading to stress at solder joint portions and electrical conduction issues.
Innovation Solution
A semiconductor device configuration with an insulating layer having an opening portion that exposes part of the electrode, allowing a connection auxiliary material to flow away and facilitate contact between electrodes and inter-device connection terminals, reducing the aspect ratio of the opening portion and using a raised portion on the electrode to ensure effective material flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If solder balls are arranged in part of an interconnect substrate located outside a semiconductor element to reduce thickness, then the thickness of the mounting structure is reduced, but the semiconductor device becomes greatly warped due to thermal expansion coefficient differences
Solution Approach 1:
The patent applies local quality by creating an asymmetric bonding area configuration where the lower bonding area (between first semiconductor device and substrate) is larger than the upper bonding area (between second semiconductor device and first semiconductor device). This local differentiation in bonding area distribution compensates for thermal expansion differences and prevents warping while maintaining reduced thickness.
2Stress or pressure
If bonding area of lower semiconductor device is reduced to be smaller than bonding area of upper semiconductor device to manage stress, then stress distribution is improved, but solder balls separate from electrodes during reflow process due to heat generation and warping
Solution Approach 1:
The patent implements asymmetry by configuring the bonding areas such that the lower bonding area is intentionally made larger than the upper bonding area. This asymmetric configuration creates a stress distribution that prevents excessive warping during reflow while ensuring solder balls remain properly positioned and connected to electrodes, thereby maintaining connection reliability.
3Ease of manufacture
If semiconductor devices are greatly warped, then manufacturing becomes more difficult due to stress application during multilayer formation, but changing bonding areas alone cannot prevent solder ball separation during reflow
Solution Approach 1:
The patent applies parameter changes by optimizing the bonding area dimensions and their asymmetric ratio to simultaneously reduce warping (improving manufacturability) and prevent solder ball separation (maintaining reliability). The specific parameter configuration of bonding areas creates a balanced stress distribution that addresses both concerns.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration prevents or reduces defective connections and enhances the reliability of the electrical connection between semiconductor devices by ensuring proper contact and adhesion, even with reduced thickness and aspect ratios.
Implementation Method 1
an insulating layer which is provided on the upper surface of the first interconnect substrate and has an opening portion through which part of the first electrode is exposed
Implementation Method 2
the thermal expansion coefficient is different between the semiconductor element and the interconnect substrate, and thus, the semiconductor device is warped during fabrication
Implementation Method 3
heat generation in a reflow process in which the two semiconductor devices are connected together. Due to the heat generation in the reflow process, each of the two semiconductor devices is warped, and then, is freely deformed
Data Source
AI summary
A semiconductor device includes a first semiconductor device and second semiconductor device stacked on the first semiconductor device. The first semiconductor device includes a first interconnect substrate, a first semiconductor element provided on an upper surface of the first interconnect substrate, a first electrode provided on the upper surface of the first interconnect substrate, and an insulating layer having an opening portion through which part of the first electrode is exposed. The second semiconductor device includes a second interconnect substrate, a second semiconductor element provided on an upper surface of the second interconnect substrate, a second electrode provided on a lower surface of the second interconnect substrate, and an inter-device connection terminal connected to the second electrode. Part of the first electrode exposed through the opening portion has a smaller area than an area of the opening portion.