Stacked Semiconductor Device Wiring for Power Gating
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Solution Overview
Problem
Current semiconductor device design methods, particularly for oxide semiconductor transistors, face challenges in achieving efficient power gating and high-frequency operation due to limitations in wiring resistance and transistor off-state current, which affect power consumption and integration density.
Innovation Solution
A semiconductor device with stacked element layers and optimized wiring layers, utilizing transistors with oxide semiconductor channels and conductors like tungsten and copper, allows for efficient power gating and high-frequency operation by reducing wiring resistance and parasitic capacitance, enabling low power consumption and high integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If oxide semiconductor transistors are used to achieve low off-state current, then power consumption is reduced, but wiring resistance and parasitic capacitance limit high-frequency operation
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional stacked wiring layers, enabling signals to travel through multiple vertical layers simultaneously. This dimensional change reduces the effective path length and resistance while maintaining low parasitic capacitance, thereby enabling high-frequency operation despite using oxide semiconductor transistors with low off-state current.
Solution Approach 2:
The patent employs composite wiring structures combining different conductive materials with optimized resistance and capacitance characteristics. By using materials with complementary properties in different wiring layers, the design achieves both low resistance for power efficiency and controlled parasitic capacitance for high-frequency performance.
2Loss of energy
If more wiring layers are added to reduce resistance, then power consumption decreases, but device complexity increases
Solution Approach 1:
The patent divides the wiring system into multiple specialized layers, each optimized for specific functions (power, ground, signal, control). This segmentation allows independent optimization of each layer's characteristics, reducing overall resistance and power consumption while maintaining manageable complexity through functional modularity.
Solution Approach 2:
The stacked wiring layers serve multiple functions simultaneously: power distribution, signal transmission, heat dissipation, and electromagnetic shielding. This multi-functionality reduces the need for additional dedicated structures, thereby lowering overall device complexity while achieving low power consumption.
3Quantity of substance
If oxide semiconductor transistors are used for power gating, then integration density improves, but design and manufacturing complexity increases
Solution Approach 1:
The patent optimizes key parameters of oxide semiconductor transistors including channel width, length, and thickness to achieve desired threshold voltages and off-state currents. By carefully controlling these parameters, the design achieves high integration density while maintaining compatibility with existing manufacturing processes and design tools.
Data Source
AI summary
To provide a semiconductor device including element layers that are stacked. A first wiring layer and a second wiring layer are stacked between a first element layer and a second element layer. A third wiring layer and a fourth wiring layer are stacked over the second element layer. Transistors of logic cells are provided in the first element layer. Wirings of the logic cells are provided in the first wiring layer or the second wiring layer. Input ports and output ports of the logic cells are provided in the third wiring layer. The input port of one of the logic cells is connected to the output port of another logic cell through the wiring of the third wiring layer or the fourth wiring layer. Connecting the logic cells through the wiring layers over the second element layer improves the efficiency of steps of arranging and connecting the logic cells.