Stacked Image Sensor Bonding Layout for Shading Reduction

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Solution Overview

Problem

Existing photoelectric conversion apparatuses lack an optimal arrangement of metal bonding portions between stacked chips, which affects the device's performance and efficiency in image sensing and other applications.

Innovation Solution

A photoelectric conversion apparatus with a specific arrangement of metal bonding portions between first and second semiconductor element layers, where the number of bonding portions overlapping a first pixel block is fewer than those overlapping a second pixel block, optimizing the interconnection resistance and improving the device's properties.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If metal bonding portions are arranged uniformly across all pixel blocks, then manufacturing is simplified, but interconnection resistance differences cause image degradation such as shading

Engineering Contradiction:
Improvebonding arrangement simplicityVSAvoidimage quality uniformity
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent applies local quality by varying the number of metal bonding portions according to the specific characteristics of each pixel block. Different pixel blocks are assigned different numbers of bonding portions based on their distance from signal processing circuits, their functional requirements, or thermal characteristics. This localized optimization ensures that each region receives the appropriate level of interconnection, reducing resistance differences and preventing shading artifacts while maintaining manufacturing feasibility through systematic variation rather than complete uniformity.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the parameter of metal bonding portion quantity across different pixel blocks. By adjusting the number of bonding portions as a variable parameter rather than keeping it constant, the invention optimizes interconnection resistance for different regions. This parameter variation allows closer pixel blocks to have fewer bonding portions while distant blocks have more, balancing the electrical characteristics across the image sensor and eliminating shading effects.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the number of metal bonding portions is increased, then interconnection resistance is reduced, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improveinterconnection resistanceVSAvoidbonding portion arrangement
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies partial action by providing metal bonding portions only where necessary to achieve optimal interconnection resistance. Instead of uniformly increasing the number of bonding portions across all pixel blocks, the invention strategically places additional bonding portions only in regions that require them, such as pixel blocks farther from signal processing circuits or those with higher current demands. This selective approach reduces overall device complexity while maintaining reliability where needed.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentEP3929987B1Photoelectric conversion apparatus, photoelectric conversion system, and movable body
Publication Date: 2024.03.06 CANON KK
  • EP3929987B1 patent drawingFigure 1
  • EP3929987B1 patent drawingFigure 2A~2B
  • EP3929987B1 patent drawingFigure 2C

AI summary

A photoelectric conversion apparatus includes a first chip including a first semiconductor element layer and a second chip including a second semiconductor element layer, the first chip and the second chip are bonded by a plurality of metal bonding portions between the first semiconductor element layer and the second semiconductor element layer, the plurality of pixel circuits includes a first pixel block including n (n is an integer of 3 or more) pixel circuits, and a second pixel block, the plurality of metal bonding portions includes a first metal bonding portion connecting the first semiconductor element layer and the second semiconductor element layer, wherein an arrangement pattern in the first pixel block of the first metal bonding portions arranged at positions overlapping the first pixel block in a planar view and an arrangement pattern in the second pixel block of the first metal bonding portions arranged at positions overlapping the second pixel block in a planar view are different.