Stacked Image Sensor Comparator Layout for Low-Lag Readout
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Solution Overview
Problem
In layered imaging devices, smaller pixels require smaller AD converter circuits, leading to increased time lags when handling multiple pixels, causing distortion or prolonged image readout times, especially when imaging moving objects.
Innovation Solution
A stacked imaging device structure with a pixel and comparing unit on the upper substrate and a storage unit on the lower substrate, utilizing transistors with varying power supplies and configurations, such as NMOS or PMOS, to optimize circuit size and performance, allowing for efficient signal processing and reduced size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If one AD converter circuit is shared by more than one pixel, then the device size is reduced, but the time lag among pixels increases causing distortion or prolonged readout time
Solution Approach 1:
The imaging device is divided into multiple independent imaging units, each with its own dedicated AD converter circuit. This segmentation allows each pixel to have immediate access to its own converter, eliminating the time lags that occur when pixels share a common converter, while keeping each unit compact enough to maintain overall device miniaturization.
Solution Approach 2:
The patent transitions from a planar layout where pixels and converters are arranged side-by-side to a three-dimensional stacked architecture. Multiple imaging units are vertically stacked, allowing each unit to have its own converter without increasing the horizontal footprint. This dimensional change enables reduced device area while maintaining dedicated converter circuits for each pixel.
2Productivity
If pixels are made smaller to increase pixel count, then image quality and processing speed are improved, but the AD converter circuits must also be made smaller which increases time lags
Solution Approach 1:
By segmenting the device into multiple independent imaging units with dedicated converters, the system can process multiple pixels simultaneously without the time lags inherent in shared converter architectures. This enables high processing speed even with miniaturized pixels and converters.
Solution Approach 2:
The patent uses replicated copies of the imaging unit structure, where each unit contains a pixel and its corresponding AD converter circuit. This copying approach allows parallel processing of multiple pixels, maintaining fast processing speeds despite the small size of individual components.
Data Source
AI summary
The present technology relates to an imaging device that can reduce the size thereof, and to an electronic apparatus.An upper substrate and a lower substrate are stacked. A pixel and a comparing unit that compares the voltage of a signal from the pixel with the ramp voltage are provided on the upper substrate, the ramp voltage varying with time. A storage unit that stores a code value obtained at a time when a comparison result from the comparing unit is inverted is provided on the lower substrate. The comparing unit is formed with a transistor that receives the voltage of the signal from the pixel at the gate, receives the ramp voltage at the source, and outputs a drain voltage. Accordingly, the imaging device can be made smaller in size. The present technology can be applied to image sensors.