Stacked Image Sensor Comparator Layout for Low-Lag Pixel Readout
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In layered imaging devices, smaller pixels require smaller AD converter circuits, leading to increased time lags when handling multiple pixels, causing distortion or prolonged image reading times, especially when imaging moving objects.
Innovation Solution
A stacked imaging device structure with a pixel and comparing unit on the upper substrate and a storage unit on the lower substrate, utilizing transistors with different power supply voltages and configurations to optimize circuit size and performance, allowing for efficient signal processing and reduced size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If one AD converter circuit is shared by more than one pixel, then the circuit size is reduced, but the time lag among pixels increases causing distortion or prolonged reading time
Solution Approach 1:
The patent divides the imaging device into multiple independent imaging units, where each imaging unit contains its own dedicated AD converter circuit. This segmentation ensures that each pixel within an imaging unit can be processed simultaneously without time lags, while the overall device size is controlled by having a limited number of imaging units rather than one large shared circuit for all pixels.
2Productivity
If pixels are made smaller to increase pixel count, then image quality and processing speed are improved, but the AD converter circuits must also be made smaller which increases time lags
Solution Approach 1:
The imaging device is divided into multiple imaging units with dedicated AD converter circuits in each unit. This allows simultaneous processing of multiple pixels across different imaging units, maintaining high processing speed even when individual pixels are made smaller and more numerous.
Solution Approach 2:
The patent transitions from a two-dimensional arrangement where all pixels compete for shared circuits to a three-dimensional stacked architecture where multiple imaging units are vertically arranged. This dimensional change allows parallel processing paths, reducing time lags while accommodating higher pixel counts through increased vertical integration rather than horizontal expansion.
3Measurement precision
If the number of pixels is increased, then image quality is improved, but the device size increases
Solution Approach 1:
The patent employs a three-dimensional stacked architecture where multiple imaging units are vertically arranged in layers. This allows a high density of pixels to be packed into a compact footprint by utilizing the vertical dimension, thereby increasing image quality through higher pixel counts without proportionally increasing the horizontal device area.
Solution Approach 2:
The imaging device uses a nested structure where imaging units containing pixels and their dedicated AD converter circuits are stacked vertically. Each imaging unit is self-contained and can be thought of as a nested module within the overall device structure, allowing efficient space utilization and high pixel density in a compact form factor.
Data Source
AI summary
The present technology relates to an imaging device that can reduce the size thereof, and to an electronic apparatus.An upper substrate and a lower substrate are stacked. A pixel and a comparing unit that compares the voltage of a signal from the pixel with the ramp voltage are provided on the upper substrate, the ramp voltage varying with time. A storage unit that stores a code value obtained at a time when a comparison result from the comparing unit is inverted is provided on the lower substrate. The comparing unit is formed with a transistor that receives the voltage of the signal from the pixel at the gate, receives the ramp voltage at the source, and outputs a drain voltage. Accordingly, the imaging device can be made smaller in size. The present technology can be applied to image sensors.