Stacked Image Sensor Architecture for Reduced Interconnect Noise
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Solution Overview
Problem
Complementary metal-oxide semiconductor (CMOS) image sensors face poor noise performance due to reduced sizes of pixel devices and increased total conductive area of the interconnect structure, which affects the active region and noise levels.
Innovation Solution
A low-noise image sensor design featuring stacked semiconductor substrates, where a readout transistor is disposed on a vertically spaced second semiconductor substrate, allowing for a larger size and reducing the total conductive area of the interconnect structure, thereby improving noise performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the readout transistor is disposed on the same semiconductor substrate as the pixel devices, then the device complexity is reduced, but the total conductive area of the interconnect structure increases leading to poor noise performance
Solution Approach 1:
The patent applies vertical stacking to move the readout transistor from the same plane as pixel devices to a different semiconductor substrate layer. This dimensional transition reduces the horizontal interconnect distance and total conductive area, thereby improving noise performance while maintaining device functionality through vertical integration.
2Productivity
If the pixel devices are reduced in size to increase pixel density, then the productivity is improved, but the noise performance deteriorates
Solution Approach 1:
By transitioning to vertical stacking architecture, the patent enables smaller pixel devices to be implemented without proportionally increasing interconnect area. The vertical separation of readout transistors on a different substrate layer reduces the horizontal conductive path, allowing higher pixel density while maintaining acceptable noise performance.
3Object-affected harmful factors
If the interconnect structure conductive area is reduced to improve noise performance, then the noise performance is improved, but the device complexity increases due to stacked substrates
Solution Approach 1:
The patent reduces noise by vertically stacking substrates to minimize horizontal interconnect area. While this introduces multi-layer complexity, it achieves superior noise performance by fundamentally reconfiguring the spatial relationship between pixel devices and readout transistors, with the trade-off justified by the noise reduction benefits.
Data Source
AI summary
Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a first semiconductor substrate having a photodetector and a floating diffusion node. A transfer gate is disposed over the first semiconductor substrate, where the transfer gate is at least partially disposed between opposite sides of the photodetector. A second semiconductor substrate is vertically spaced from the first semiconductor substrate, where the second semiconductor substrate comprises a first surface and a second surface opposite the first surface. A readout transistor is disposed on the second semiconductor substrate, where the second surface is disposed between the transfer gate and a gate of the readout transistor. A first conductive contact is electrically coupled to the transfer gate and extending vertically from the transfer gate through both the first surface and the second surface.