Stacked Image Sensor Structure for Smaller Pixel Pitch
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Solution Overview
Problem
CMOS image sensors face reduced performance due to space constraints from pixel transistors, which limit the photosensitive area and make it challenging to reduce pixel pitch, as these transistors are integrated along the semiconductor substrate with photodetectors.
Innovation Solution
The pixel transistors are arranged on a separate substrate from the photodetectors and transfer transistors, allowing for increased space for photodetectors and easier reduction of pixel pitch, with a shared floating diffusion region and trench isolation layer to enhance performance and reduce cross-talk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If pixel transistors are integrated along the semiconductor substrate with photodetectors, then device functionality is complete, but photosensitive area is reduced and pixel pitch reduction becomes challenging
Solution Approach 1:
The device is divided into two separate substrates: a first substrate containing photodetectors and a second substrate containing pixel transistors. This segmentation allows the photosensitive area on the first substrate to be maximized without being constrained by transistor space requirements, while still achieving complete device functionality through inter-substrate integration.
Solution Approach 2:
The solution transitions from a planar integration approach to a three-dimensional stacked architecture. By placing photodetectors on one substrate and transistors on another substrate in vertical stacking, the patent achieves spatial separation that increases photosensitive area while maintaining compact overall device footprint through vertical integration.
2Length of moving object
If pixel transistors are integrated on the same substrate as photodetectors, then manufacturing is simplified, but pixel pitch reduction becomes difficult
Solution Approach 1:
By segmenting the device into separate substrates for photodetectors and transistors, each substrate can be optimized independently for its specific function. The first substrate can be designed with minimal pixel pitch constraints since transistors are not competing for the same planar space, enabling smaller pixel pitch while maintaining manufacturing feasibility through separate substrate processing followed by integration.
Solution Approach 2:
The vertical stacking architecture enables pixel pitch reduction by moving transistor placement to a different spatial dimension (vertical layering rather than horizontal arrangement). This allows tighter horizontal spacing of pixels while transistors are accommodated on the second substrate, achieving smaller pixel pitch without compromising manufacturing ease.
3Length of moving object
If photodetectors are closely spaced to reduce pixel pitch, then device compactness is improved, but space for pixel transistors is insufficient
Solution Approach 1:
The patent segments the device architecture into two independent substrates, allowing photodetectors to be closely spaced on the first substrate to achieve compact pixel pitch, while transistors are placed on the second substrate where space is not constrained by horizontal pixel spacing requirements.
Solution Approach 2:
By transitioning to a vertical stacked architecture, the patent resolves the spatial conflict between closely spaced photodetectors and transistor placement. Photodetectors achieve compact horizontal spacing on the first substrate, while transistors are accommodated on the second substrate in the vertical dimension, enabling both compact pixel pitch and complete transistor functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the performance of the integrated chip by increasing the photosensitive area and allowing for a more compact pixel design, enhancing focusing speed and conversion gain while reducing floating diffusion capacitance.
Implementation Method 1
The pixel includes a first photodetector and a second photodetector in the first substrate
Data Source
AI summary
An integrated chip including a first semiconductor substrate. The first semiconductor substrate includes a doped region. A first photodetector and a second photodetector are in the first semiconductor substrate. A trench isolation layer at least partially surrounds the first photodetector and the second photodetector and extends between the first photodetector and the second photodetector. The trench isolation layer has a first pair of sidewalls. The first semiconductor substrate extends from the first photodetector, between the first pair of sidewalls, to the second photodetector. The doped region is between the first pair of sidewalls. The first photodetector and a first gate partially form a first transistor. The second photodetector and a second gate partially form a second transistor. A second semiconductor substrate is over the first gate and the second gate. A third transistor is along the second semiconductor substrate. The third transistor is coupled to the first transistor.