Stacked Image Sensor Readout for Rolling Shutter Continuity
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Solution Overview
Problem
3D-stacked image sensors face challenges with rolling shutter discontinuity and difficulties in transmitting digital data due to sub-column parallel readout architectures, which affect image quality and frame rate, especially when windowing is applied.
Innovation Solution
The proposed solution involves a stacked image sensor design where each pixel column is split into sub-columns, with each sub-column connected to a dedicated stage in the control logic tier, allowing for sequential readout and parallel operation of analog-to-digital converters, reducing rolling shutter discontinuity and improving frame rate through efficient digital code transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sub-column parallel readout architecture is used, then frame rate is improved through increased parallelism, but rolling shutter discontinuity occurs causing image distortion
Solution Approach 1:
The pixel array is divided into multiple sub-columns, each with its own dedicated ADC stage. This segmentation allows parallel readout of multiple sub-columns simultaneously, increasing frame rate while maintaining image quality through proper sequencing control.
Solution Approach 2:
The readout architecture dynamically sequences through sub-columns in a controlled manner, adjusting the readout pattern to avoid rolling shutter discontinuity while maintaining high parallelism for high frame rates.
2Speed
If sub-column parallel readout with dedicated ADCs per sub-column is used, then readout speed is improved, but device complexity increases due to multiple independent ADCs
Solution Approach 1:
Multiple ADC stages are merged into a single shared ADC resource that serves all sub-columns. The ADC is time-multiplexed across different sub-columns, reducing the total number of ADCs while maintaining high readout speed through efficient resource sharing.
Solution Approach 2:
A single ADC is designed to serve multiple sub-columns universally through time-multiplexed operation. The same ADC hardware performs conversion for different sub-columns at different times, eliminating the need for dedicated ADCs per sub-column.
3Productivity
If more sub-columns are used to increase parallelism, then frame rate is improved, but difficulty in transmitting digital data to periphery increases
Solution Approach 1:
Digital data from multiple sub-columns is merged into a single transmission path. The ADC output is sequentially or time-multiplexed to a single digital interface, simplifying data transmission to the periphery while maintaining high frame rate through efficient data aggregation.
4Productivity
If windowing is applied to reduce array resolution, then frame rate is improved, but number of sub-columns and ADCs is reduced which may not be desirable
Solution Approach 1:
The readout architecture dynamically adapts to windowing configurations by adjusting which sub-columns are activated and how the ADC time-multiplexing is configured. This maintains readout configuration flexibility and adaptability even when windowing is applied to improve frame rate.
Data Source
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AI summary
An image sensor is proposed to have a stack with at least a pixel array tier (PXT) and a control logic tier (CLT). The pixel array tier (PXT) comprises an array of pixels which are arranged into pixel columns (n), each pixel column (n) comprising a number of N sub-columns: Each sub-column is denoted by N(n,i) with 1 ≤ i ≤ N. The control logic tier (CLT) comprises an array of analog-to-digital-converters (ADC(m)) which are arranged into ADC columns (m), wherein each analog-to-digital converter (ADC(m)) comprises a number of M stages. Each stage is denoted by M(m,j) with 1 ≤ j ≤ M, Furthermore, each respective sub-column N(n,i) is electrically connected to a dedicated stage M(m,j=i) and the stages M(m,j) are electrically interconnected to form the analog-to-digital converters (ADC(m)), respectively. The control logic tier (CLT) is arranged to sequentially read out the sub-columns N(n,i), wherein the stages M(m,j=i) dedicated to the sub-columns N(n,i) are arranged as input stages to sequentially receive signal levels of the pixels in the sub-columns N(n,i), respectively. The input stages are arranged to perform on the sequentially received signal levels a coarse first analog-to-digital conversion. The remaining stages M(m,j≠i) are arranged to sequentially perform finer analog-to-digital conversions of the received signal levels.