Stacked Imaging Sensor Via Structure for Fewer Interconnect Steps
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Solution Overview
Problem
Existing semiconductor devices with stacked structures require further reduction in manufacturing steps and costs, particularly in the electrical connection of multiple semiconductor substrates.
Innovation Solution
The implementation of a through via that penetrates an embedded oxide film during element isolation of a semiconductor element, allowing for simultaneous formation with contact electrodes, reducing the need for additional processing steps and dedicated devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through via is formed separately from contact electrodes using dedicated devices, then electrical connection between substrates is achieved, but manufacturing steps and device complexity increase
Solution Approach 1:
The patent combines the formation of through vias and contact electrodes into a single integrated process step. Both structures are formed simultaneously using the same etching and filling operations, eliminating the need for separate dedicated devices and process steps while maintaining reliable electrical connections between stacked substrates
Solution Approach 2:
The same process equipment and methodology are used to form both through vias (for substrate interconnection) and contact electrodes (for vertical connections). This multi-functional approach allows a single process step to accomplish multiple electrical connection tasks, reducing manufacturing complexity
2Reliability
If through via penetrates deep into semiconductor layer, then electrical connection is established, but manufacturing precision and process difficulty increase
Solution Approach 1:
The patent creates different local structures within the same semiconductor layer by forming contact holes that stop at the semiconductor layer interface, while through vias continue penetrating into the underlying substrate. This local differentiation allows precise control of via depth for different connection purposes without compromising manufacturing precision
3Area of stationary object
If stacked structure is implemented, then chip area is reduced and power consumption is suppressed, but manufacturing steps increase
Solution Approach 1:
The patent merges the through via formation process with the contact electrode formation process in stacked structures. By using the same etching and filling steps for both structures, the manufacturing complexity is significantly reduced while maintaining the space-efficient stacked architecture
Data Source
AI summary
The present disclosure relates to a semiconductor device, a manufacturing method, an imaging element, and an electronic device capable of reducing manufacturing steps in a stacked structure obtained by stacking two or more semiconductor substrates. The semiconductor device has a stacked structure obtained by stacking at least a first semiconductor substrate in which a first wiring layer is stacked on a first semiconductor layer and a second semiconductor substrate in which a second wiring layer is stacked on a second semiconductor layer. Then, a through via which electrically connects the first semiconductor substrate and the second semiconductor substrate to each other and penetrates at least the first semiconductor layer is formed in an embedded oxide film formed when element isolation of a semiconductor element formed in the first semiconductor layer is performed. The present technology is applicable to, for example, a stacked semiconductor device.