Stacked Sheet Transistor Gate Structure for Short-Channel Control
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Solution Overview
Problem
Current semiconductor devices face challenges in scaling and improving current control capabilities while effectively suppressing short channel effects, particularly in multi-gate transistors with three-dimensional channels.
Innovation Solution
The semiconductor device design includes a lower pattern and sheet patterns spaced apart, with a gate structure surrounding the sheet patterns and a source/drain pattern in contact, featuring a gate electrode extending perpendicular to the sheet patterns and a gate spacer that overlaps the sheet patterns, enhancing contact surface area and width for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistor with three-dimensional channels is used, then scaling is readily performed and current control capability is improved, but device complexity increases
Solution Approach 1:
The active pattern is segmented into multiple sheet patterns (first sheet pattern, second sheet pattern, etc.) stacked in the third direction, with each sheet pattern forming a separate channel. This segmentation enables multi-gate control while maintaining a manageable structural organization through the lower pattern and gate structure.
Solution Approach 2:
The invention transitions from two-dimensional planar channels to three-dimensional stacked sheet patterns in the third direction. Multiple sheet patterns are arranged vertically, allowing gate structures to wrap around and control channels from multiple directions, achieving superior scaling and current control through dimensional enhancement.
2Area of stationary object
If gate length is not increased, then device area is maintained, but current control capability deteriorates
Solution Approach 1:
Instead of increasing gate length in the second direction, the invention adds vertical stacking of sheet patterns in the third direction. This creates multiple channels that can be controlled by gates wrapping around from multiple directions, improving current control capability without increasing the planar device area.
Solution Approach 2:
The gate structure is designed to wrap around and surround each sheet pattern, with gate electrodes positioned on multiple sides of the channel. This nested configuration allows the gate to control the channel from multiple directions simultaneously, enhancing current control without requiring longer gate lengths.
3Reliability
If sheet pattern width is increased, then current control is improved, but contact surface area between sheet pattern and source/drain pattern decreases
Solution Approach 1:
The invention compensates for reduced contact surface area by utilizing the third direction (vertical stacking). Multiple sheet patterns are stacked vertically, providing additional contact interfaces between source/drain patterns and channels. The increased number of stacked sheets maintains total contact area even when individual sheet widths are increased for better current control.
Data Source
AI summary
A semiconductor device includes an active pattern which includes a lower pattern, and a sheet pattern that is spaced apart from the lower pattern in a first direction, a gate structure on the lower pattern that includes a gate electrode that surrounds the sheet pattern, the gate electrode extending in a second direction that is perpendicular to the first direction, and a source/drain pattern on the lower pattern and in contact with the sheet pattern. A contact surface between the sheet pattern and the source/drain pattern has a first width in the second direction, and the sheet pattern has a second width in the second direction that is greater than the first width.