Stacked Si CMOS Device with Vertical Channel Integration
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Solution Overview
Problem
Current methods for manufacturing Si-based high-mobility CMOS devices struggle to efficiently co-integrate high-mobility germanium or silicon-germanium and III-V semiconductor channels on a silicon substrate, limiting electrical performance and layout efficiency.
Innovation Solution
A method involving selective area growth to stack III-V semiconductor and germanium or silicon-germanium channel layers on a silicon substrate, using sacrificial layers and oxide layers to control growth and confine defects, allowing for vertical alignment of n/p channels and improved electrostatic properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-mobility germanium or silicon-germanium and III-V semiconductor channels are co-integrated side by side on a silicon substrate, then electrical performance is improved, but layout efficiency is reduced
Solution Approach 1:
The patent transitions from horizontal side-by-side integration to vertical stacked integration of germanium and III-V semiconductor channel layers. This dimensional change from 2D lateral arrangement to 3D vertical stacking allows both high-mobility materials to be integrated on the same silicon substrate while significantly improving layout efficiency by reducing the area occupied by the device structure.
2Area of stationary object
If selective area growth is used to stack channel layers, then layout efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct stages: forming sacrificial layers in trenches, depositing oxide layers, selectively removing sacrificial material, and performing selective area epitaxial growth. This segmentation of the complex manufacturing process into manageable steps makes the vertical stacking approach feasible while maintaining layout efficiency.
Solution Approach 2:
Sacrificial layers are introduced as intermediary structures that enable the selective area growth process. These temporary structures are deposited, covered with oxide layers, and selectively removed to define the growth regions for the stacked channel layers. The sacrificial layers act as mediators that facilitate the complex stacking process without requiring direct complex patterning of the channel materials themselves.
3Area of stationary object
If vertical stacking of channel layers is implemented, then layout efficiency and electrostatic properties are improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by creating spatially varying structures: oxide layers are deposited selectively over sacrificial layers in specific regions, and selective area growth is performed only in defined trenches. This local differentiation allows precise control over where each channel layer forms, enabling vertical stacking with the required manufacturing precision through localized process control rather than requiring high precision across the entire substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the electrostatic properties and layout efficiency of CMOS devices by enabling vertical alignment of n/p channels, improving electrical performance and manufacturing efficiency.
Implementation Method 1
replacing the first dummy layer with III-V semiconductor material by etching the sacrificial material via holes made in the first oxide layer followed by selective area growth with the III-V semiconductor material
Implementation Method 2
replacing the second dummy layer with germanium or silicon-germanium by etching the sacrificial material via holes made in the second oxide layer followed by selective area growth with germanium or silicon-germanium
Data Source
AI summary
A device and method for manufacturing a Si-based high-mobility CMOS device is provided. The method includes the steps of: (i) providing a silicon substrate having a first insulation layer on top and a trench into the silicon; (ii) manufacturing a III-V semiconductor channel layer above the first insulation layer by depositing a first dummy layer of a sacrificial material, covering the first dummy layer with a first oxide layer, and replacing the first dummy layer with III-V semiconductor material by etching via holes in the first oxide layer followed by selective area growth; (iii) manufacturing a second insulation layer above the III-V semiconductor channel layer and uncovering the trench; (iv) manufacturing a germanium or silicon-germanium channel layer above the second insulation layer by depositing a second dummy layer of a sacrificial material, covering the second dummy layer with a second oxide layer, and replacing the second dummy layer with germanium or silicon-germanium by etching via holes in the second oxide layer followed by selective area growth.