Stacked Silicon Capacitor Structure for Compact Semiconductor Packages
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Solution Overview
Problem
The increasing demand for portable electronic devices has driven the need for miniaturization and weight reduction of electronic components, while also requiring increased memory capacity, which poses a challenge in efficiently arranging semiconductor chips and capacitors within limited semiconductor package structures.
Innovation Solution
A semiconductor package design that incorporates a stacked silicon capacitor with solder bump pads on both the top and bottom surfaces, allowing for increased capacitance and flexibility in circuit design, while maintaining a compact form factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Weight of moving object
If the overall thickness of semiconductor packages is decreased to miniaturize and reduce weight, then the portable electronic devices become more compact and lighter, but the memory capacity and capacitance arrangement space is reduced
Solution Approach 1:
The patent transitions from a planar arrangement of capacitors to a three-dimensional stacked configuration. Multiple substrate structures are vertically stacked with bump pads connecting adjacent substrates, enabling capacitance to be accumulated in the vertical dimension rather than being constrained to a two-dimensional plane. This dimensional change allows increased capacitance within a reduced footprint area.
Solution Approach 2:
The patent implements a nested structure where multiple substrate structures are stacked and interconnected through bump pads. Each substrate structure contains capacitor elements, and the stacking arrangement creates a nested configuration where substrates are positioned one above another, similar to nested dolls. This nesting enables efficient space utilization and increased capacitance density.
2Area of stationary object
If various structures are applied to efficiently arrange semiconductor chips and passive devices within limited package structure, then the space utilization is improved, but the circuit design complexity increases
Solution Approach 1:
The patent divides the capacitor structure into multiple discrete substrate structures, each containing capacitor elements and bump pads. This segmentation allows independent design and arrangement of each substrate unit, simplifying the overall circuit design process while achieving efficient space utilization through modular stacking. Each segment can be independently optimized and then combined.
Solution Approach 2:
The substrate structures serve multiple functions: they provide mechanical support, contain capacitor elements for electrical storage, and provide bump pads for electrical interconnection. This multi-functionality reduces the need for separate components and simplifies circuit design by consolidating multiple functions into a single integrated structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves increased electrostatic capacity and reduced equivalent series resistance, enabling more efficient use of space within the semiconductor package, thereby supporting the demands for miniaturization, weight reduction, and enhanced memory capacity in portable electronic devices.
Implementation Method 1
neighboring silicon substrates are bonded to each other through the upper bump pad and the lower bump pad facing each other
Data Source
AI summary
A semiconductor package includes a printed circuit board including a circuit pattern and a silicon capacitor connected to the circuit pattern, a semiconductor chip mounted on the printed circuit board, and an external connection terminal attached below the printed circuit board, wherein the silicon capacitor is a stacked structure of a plurality of substrate structures, each of the plurality of substrate structures includes a silicon substrate, a capacitor structure, a via electrode penetrating through the silicon substrate around the capacitor structure, an upper bump pad disposed on top of the via electrode, and a lower bump pad disposed below the via electrode, and, in the plurality of substrate structures, neighboring silicon substrates are bonded to each other through the upper bump pad and the lower bump pad facing each other.