Stacked Silicon Die Architecture with Mixed Flipchip and Wirebond Interconnect
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Solution Overview
Problem
3D stacked semiconductor devices face x-height and x-y area limitations in system-on-a-chip (SoC) package-on-package (PoP) implementations, particularly due to the increased vertical interconnect area and z-height caused by ball grid array (BGA) solder connections, which hinder miniaturization and efficiency.
Innovation Solution
The solution involves a stacked semiconductor die package that uses flip chip interconnects and wire bond interconnects to vertically stack dies, eliminating the need for two package constructions and reducing the overall volume by using an active silicon interposer and encapsulation layer, thereby minimizing z-height and footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ball grid array (BGA) solder connections are used to stack dies vertically, then the vertical interconnect area and z-height increase, but this causes x-height and x-y area limitations that hinder miniaturization
Solution Approach 1:
The patent merges flip chip interconnect technology with wire bond interconnect technology into a hybrid packaging architecture. The flip chip provides robust vertical interconnection between stacked dies, while wire bonds provide additional interconnect pathways without requiring large BGA solder connection areas, thereby reducing overall package volume while maintaining connection reliability
Solution Approach 2:
The patent transitions from a two-dimensional BGA solder connection layout to a three-dimensional hybrid interconnect structure where wire bonds extend vertically and laterally to provide interconnect pathways that occupy less planar area, effectively reducing the x-y footprint and overall package volume
2Adaptability or versatility
If two separate package constructions are used for stacked dies, then interconnect functionality is achieved, but package surface area and z-height are significantly increased
Solution Approach 1:
The patent combines what would traditionally be two separate package constructions into a single integrated package structure. The flip chip interconnects directly attach dies to the substrate in a stacked configuration, while wire bonds provide additional interconnect pathways within the same package volume, eliminating the need for separate package constructions and reducing overall z-height
Solution Approach 2:
The hybrid interconnect structure serves multiple functions within a single package: flip chip connections provide primary vertical interconnect between dies, wire bonds provide additional interconnect pathways and signal routing, and the encapsulation provides mechanical support and protection. This multi-functional integration reduces the need for separate specialized packages
3Reliability
If ball grid array (BGA) solder connections are used for die stacking, then vertical interconnect is achieved, but x-y area footprint is increased
Solution Approach 1:
The patent merges flip chip interconnect technology with wire bond interconnect technology into a hybrid packaging architecture. The flip chip provides robust vertical interconnection between stacked dies, while wire bonds provide additional interconnect pathways without requiring large BGA solder connection areas, thereby reducing overall package volume while maintaining connection reliability
Solution Approach 2:
Wire bonds serve as an intermediary interconnect mechanism that bridges the gap between flip chip connections and external package pins. This intermediary approach provides flexible signal routing without requiring extensive BGA solder connection areas, effectively reducing the package footprint while maintaining reliable die-to-die connections
Data Source
AI summary
Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a base die disposed on an interposer. The semiconductor package also has a plurality of dies on top of one another to form a stack on the base die. Each die has a top surface and a bottom surface that is opposite from the top surface, and each die has one or more die contacts on at least one of the top surface and the bottom surface that are each electrically coupled to at least one die contact of the base die with one or more wire bonds. The semiconductor package includes a mold layer disposed over and around the plurality of dies, the base die, and the one or more wire bonds. The base die may have a first surface area that exceeds a second surface area of the plurality of stacked dies.