Stacked-Silicon Memory Arrays with Dual-Layer CMOS Circuits
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Solution Overview
Problem
Existing memory devices face challenges in reducing production costs while maintaining efficient data storage capabilities.
Innovation Solution
A memory device is designed with a stacked structure comprising multiple silicon substrates, where CMOS circuits are formed on different layers, and a memory cell array is connected to these circuits, allowing for a more efficient layout and reduced production costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional single-substrate memory device structure is used, then the device structure is simple and easy to manufacture, but the production cost cannot be reduced and data storage efficiency is limited
Solution Approach 1:
The patent transitions from a conventional planar single-substrate structure to a three-dimensional stacked multi-substrate structure. Multiple substrates are stacked vertically with memory cell arrays formed on each substrate, enabling data storage to occur in multiple layers simultaneously. This dimensional change from 2D to 3D architecture significantly increases storage capacity and efficiency while maintaining manufacturing feasibility through standardized stacking processes
2Productivity
If multiple substrates are stacked to improve data storage efficiency, then productivity increases, but the device structure becomes more complex and manufacturing becomes more difficult
Solution Approach 1:
The memory device is segmented into multiple independent substrates, each containing a complete memory cell array and associated circuits. This segmentation allows each substrate to be manufactured and tested independently before stacking, reducing the complexity of handling the entire multi-layer structure as a single unit. The modular approach simplifies the manufacturing process by breaking down the complex stacked structure into manageable, standardized components
Solution Approach 2:
Multiple substrates are nested vertically in a stacked configuration, with each substrate containing complete memory functionality. The nested arrangement allows compact integration of multiple memory layers while maintaining independent access to each layer's data storage capacity, effectively increasing overall storage efficiency without proportionally increasing device footprint or manufacturing complexity
3Device complexity
If CMOS circuits are integrated on the same substrate as memory cells, then device complexity is reduced, but manufacturing precision requirements increase and production costs rise
Solution Approach 1:
The device is segmented into separate substrates: some substrates contain only memory cell arrays while other substrates contain CMOS circuits. This segmentation eliminates the need for precise co-integration of different circuit types on the same substrate, reducing manufacturing precision requirements. Each substrate can be optimized independently for its specific function, simplifying the manufacturing process and reducing costs
Data Source
AI summary
According to one embodiment, a memory device includes a first silicon substrate, a second silicon substrate, and a memory cell array. A first CMOS circuit is formed on the first silicon substrate. The second silicon substrate is provided above the first silicon substrate in a stacking direction. A second CMOS circuit is formed on the second silicon substrate. The memory cell array is provided above the second silicon substrate in the stacking direction. The memory cell array is connected to the first CMOS circuit and the second CMOS circuit and includes a plurality of memory cells arranged in the stacking direction of the first silicon substrate and the second silicon substrate.