Stacked Silicon Passive Component Layout for Compact Semiconductor Packaging
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Solution Overview
Problem
Conventional semiconductor devices with MLCCs and chips on substrates result in larger sizes due to their side-by-side configuration, which is inefficient in terms of space utilization.
Innovation Solution
A semiconductor device design where a silicon-based passive component is stacked on top of a semiconductor component in the thickness direction, allowing for reduced size and high input/output density through the inclusion of passive structures like capacitance, resistance, and inductance, and input/output contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If MLCC and chip are disposed on substrate side by side, then input/output capabilities are maintained, but device size increases
Solution Approach 1:
The patent transitions from a planar side-by-side configuration to a three-dimensional stacked configuration. The passive component is positioned vertically above the semiconductor component, utilizing the thickness direction (Z-axis) to resolve the spatial conflict. This dimensional change allows both components to coexist within a smaller footprint area while maintaining their respective functions and input/output capabilities.
Solution Approach 2:
The patent implements a nested arrangement where the passive component structure is positioned within the vertical space above the semiconductor component. The stacked configuration allows the passive component to be effectively 'nested' in the third dimension, enabling both components to share the same lateral footprint while maintaining functional independence and input/output versatility.
2Productivity
If MLCC and chip are disposed on substrate side by side, then functional requirements are met, but space utilization efficiency decreases
Solution Approach 1:
By utilizing the vertical dimension for component stacking, the patent dramatically improves space utilization efficiency. The thickness direction is underutilized in conventional planar designs, but the stacked configuration fully exploits this dimension, allowing multiple components to occupy the same lateral space while maintaining functional integrity and reliability.
3Area of stationary object
If stacked configuration is used, then device size is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent divides the semiconductor device into distinct stacked segments: the semiconductor component at the base and the passive component above it. This segmentation allows each component to be manufactured and prepared separately, then assembled in a controlled stacking process, thereby managing manufacturing complexity while achieving compact dimensions.
Solution Approach 2:
The stacked configuration serves multiple functions simultaneously: it reduces device size, maintains input/output capabilities, and provides a scalable architecture. The universal stacking approach can be applied to various component types and can accommodate different numbers of passive components, making the manufacturing process adaptable rather than overly complex.
Data Source
Figure 1A~1B
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AI summary
A semiconductor device includes a semiconductor component and a silicon-based passive component. The silicon-based passive component is stacked on the semiconductor component in a thickness direction of the semiconductor component.