Stacked Silicon Substrate Capacitance for Voltage Droop
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Solution Overview
Problem
High current demands in computer processing units, such as Graphcore's IPU chips, lead to significant supply voltage droop issues due to parasitic resistance and inductance in circuitry, which existing capacitance solutions are insufficient to adequately address, especially in high current demand/low supply voltage structures.
Innovation Solution
A computer structure incorporating a second silicon substrate with distributed capacitance units, connected via through silicon vias to a first silicon substrate, providing a high-capacity capacitance network to mitigate supply voltage droop by using wafer-on-wafer technology, where the second substrate is thinned to have a non-self-supporting depth and the distributed capacitor units cover at least 80% of the first substrate's area, arranged in a regular array with trench capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional capacitance solutions are used, then some voltage droop mitigation is achieved, but the capacitance capacity is insufficient for high current demand structures
Solution Approach 1:
The patent transitions from planar capacitance placement to three-dimensional stacked architecture. Multiple capacitor layers are stacked vertically above the substrate, utilizing the third dimension (height/depth) to increase total capacitance capacity without occupying additional planar area. This dimensional transition enables significantly higher capacitance values needed for high current demand applications.
Solution Approach 2:
The patent implements nested capacitance structures where capacitor elements are arranged in hierarchical layers. Multiple capacitor layers are nested vertically, with each layer containing multiple capacitor units. This nested arrangement maximizes capacitance density by packing capacitor elements efficiently in both horizontal and vertical spaces.
2Reliability
If larger capacitance values are implemented, then voltage droop is reduced, but the physical area required increases
Solution Approach 1:
By stacking capacitor layers vertically, the patent achieves large total capacitance values without proportionally increasing the planar footprint. The vertical stacking allows capacitance to scale in the Z-dimension while maintaining a compact XY-plane area, effectively decoupling capacitance magnitude from planar area requirements.
Solution Approach 2:
The capacitor structure is strategically positioned and distributed across the substrate surface. Different regions may have varying capacitor densities optimized for local current demand patterns. This localized optimization ensures adequate voltage regulation where needed while minimizing total area consumption.
3Length of stationary object
If the second substrate is thinned to non-self-supporting depth, then the overall structure height is reduced, but the substrate requires support from the first substrate
Solution Approach 1:
The patent merges the second substrate with the first substrate through bonding, creating a mechanically integrated stacked structure. The two substrates are bonded together such that the first substrate provides mechanical support to the thinned second substrate, eliminating the need for the second substrate to be self-supporting while maintaining overall structural integrity.
Solution Approach 2:
A bonding layer or bonding interface acts as an intermediary between the first and second substrates. This bonding interface transfers mechanical loads and provides structural coupling, allowing the thinned second substrate to rely on the first substrate for support while maintaining electrical and mechanical connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces supply voltage undershoots, allowing for a lower initial supply voltage while maintaining a safe minimum voltage, thereby increasing clock frequency and performance without increasing dynamic power consumption.
Implementation Method 1
providing a high-capacity capacitance network to mitigate supply voltage droop
Data Source
AI summary
There is provided a computer structure comprising a first silicon substrate and a second silicon substrate. Computer circuitry configured to perform computing operations is formed in the first silicon substrate, which has a self-supporting depth and an inner facing surface. A plurality of distributed capacitance units are formed in the second silicon substrate, which has an inner facing surface located in overlap with the inner facing surface of the first substrate and is connected to the first substrate via a set of connectors arranged extending depthwise of the structure between the inner facing surfaces. The inner facing surfaces have matching planar surface dimensions. The second substrate has an outer facing surface on which are arranged a plurality of connector terminals for connecting the computer structure to a supply voltage. The second substrate has a smaller depth than the first substrate.