Stacked SLM Driver Layout for Small-Pitch High-Voltage Pixels
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Solution Overview
Problem
Spatial light modulators (SLMs) face limitations in achieving high étendue due to the size mismatch between SLM pixels and drive circuits, requiring larger transistors and higher voltages, which complicates the integration of high voltage transistors and CMOS control circuitry, especially as pixel sizes decrease.
Innovation Solution
A spatial light modulator with a 2D array of pixels and a stacked 1D array of drivers monolithically integrated on the same substrate, where each driver is electrically coupled to multiple pixels through interconnect arms and load balance arms, allowing for efficient voltage distribution and reduced RC loading, enabling smaller transistor footprints and lower drive voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the size of the modulator is reduced to achieve high étendue, then the spatial period or pitch of the SLM is reduced, but the voltage required to move or drive the electrostatically deflectable elements increases sharply
Solution Approach 1:
The patent transitions from a planar integration layout to a three-dimensional stacked architecture, placing driver circuits in separate layers above the modulator array. This vertical stacking enables compact integration while maintaining adequate spacing for high-voltage transistor operation, resolving the contradiction between small modulator size and high drive voltage requirements.
Solution Approach 2:
The patent segments the driver circuits into multiple independent driver units, each capable of driving multiple pixels through shared scan lines. This segmentation allows for modular high-voltage transistor design and reduces the area requirement per pixel while maintaining the necessary voltage levels for small-pixel operation.
2Area of moving object
If the size of the modulator is reduced to achieve high étendue, then the spatial period or pitch of the SLM is reduced, but the driver size increases due to requirement for high voltage transistors
Solution Approach 1:
By stacking driver circuits in a third dimension above the modulator plane, the patent eliminates the area conflict between small pixels and large high-voltage transistors. The vertical layering allows both small modulator pitch and adequate driver transistor size to coexist without competing for lateral space.
Solution Approach 2:
Each driver unit is designed to control multiple pixels through shared scan line structures, making the driver circuit multi-functional. This reduces the total driver area required while maintaining full control capability over the pixel array, enabling small pixel pitch without proportionally increasing driver area.
3Power
If high voltage transistors are integrated with CMOS control circuitry, then the drive capability is improved, but the device complexity increases
Solution Approach 1:
The patent divides the driver circuit into separate high-voltage transistor sections and CMOS control sections, with each section optimized for its specific function. The high-voltage drivers handle power delivery while CMOS circuits handle control logic, reducing the complexity of integrating these incompatible technologies compared to full monolithic integration.
Solution Approach 2:
The patent introduces intermediate voltage conversion circuits that bridge the CMOS control voltage levels and the high-voltage driver requirements. These intermediary stages allow standard CMOS processes to control high-voltage transistors without requiring complex mixed-signal integration, simplifying the overall device fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves high étendue while maintaining lower drive voltages and smaller transistor areas, enabling higher pixel counts and improved performance in applications like 3D printing and materials processing without the need for complex integration schemes or exotic materials.
Implementation Method 1
a voltage applied between an electrode in the deflectable element and an electrode in the substrate provided by a drive circuit integrally formed in the substrate underlying (i.e. integrated) or adjacent to the first and second light reflective surfaces (i.e. non-integrated) causes the deflectable element to be deflected towards the substrate
Implementation Method 2
the first and second light reflective surfaces have equal area and reflectivity so that in operation deflection of the electrostatically deflectable element brings light reflected from the first light reflective surface into constructive or destructive interference with light reflected from the second light reflective surface
Data Source
AI summary
A spatial light modulator (SLM) including a two-dimensional (2D) array of n rows of m pixels, and a stacked drive circuit including at least one, one-dimensional (1D) array of n*m drivers monolithically integrated on the same substrate and methods of fabricating and methods of using the same in materials processing applications are provided. Generally, each pixel includes at least one modulator, and is configured to modulate light incident thereon in response to drive signals received from the stacked drive circuit. The 1D array of the stacked drive circuit includes a single row of n*m drivers arranged adjacent to and laterally separated from the 2D array of pixels. Other embodiments are also described.