Stacked Snubber Capacitor Layout for Low-Inductance Semiconductor Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices face challenges in reducing noise and improving power conversion efficiency due to high parasitic inductance and noise generation from high frequency currents in power conversion circuits, particularly in configurations with snubber capacitors and switching elements.
Innovation Solution
The semiconductor device incorporates a capacitor between two switching elements, with electrodes facing each other in a specific direction, and a dielectric layer with a thin thickness to minimize the high frequency current path and parasitic inductance, thereby reducing noise and enhancing power conversion efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a conventional capacitor configuration is used in power conversion circuits, then the circuit can perform power conversion functions, but high parasitic inductance and noise are generated
Solution Approach 1:
The patent transitions from a conventional planar capacitor layout to a three-dimensional stacked configuration where capacitor electrodes are arranged in multiple layers above and below the substrate. This vertical stacking in the Z-dimension reduces the horizontal current path length, thereby minimizing parasitic inductance and noise generation while maintaining the power conversion function
Solution Approach 2:
The capacitor is divided into multiple electrode layers (first electrode, second electrode, third electrode, fourth electrode) arranged in a stacked configuration. Each electrode layer is separated by insulating layers, creating segmented capacitor units that collectively reduce the overall current path and parasitic inductance compared to a single-layer configuration
2Productivity
If the high frequency current path is long, then the capacitor can be easily manufactured, but parasitic inductance increases and power conversion efficiency decreases
Solution Approach 1:
The patent utilizes vertical stacking of capacitor electrodes in the Z-dimension to create a compact three-dimensional structure. This approach dramatically shortens the horizontal current path length while maintaining adequate capacitance, thereby reducing parasitic inductance and improving power conversion efficiency without compromising manufacturability
3Productivity
If parasitic inductance is high, then the circuit structure is simpler, but noise increases and power conversion efficiency deteriorates
Solution Approach 1:
The capacitor is segmented into multiple electrode layers (first, second, third, and fourth electrodes) with insulating layers between them. This segmentation creates multiple parallel current paths through the capacitor, effectively reducing the total parasitic inductance and noise generation while maintaining the required capacitance for power conversion
Solution Approach 2:
The patent employs a composite structure combining conductive electrode layers with insulating dielectric layers in a stacked configuration. This composite architecture optimizes the balance between capacitance, parasitic inductance, and noise reduction, achieving superior power conversion efficiency compared to conventional single-material capacitor designs
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in a shorter high frequency current path, reduced parasitic inductance, and decreased noise, leading to improved power conversion efficiency and noise reduction.
Implementation Method 1
a dielectric layer arranged between the first wiring layer and the second wiring layer... to minimize the high frequency current path and parasitic inductance
Data Source
AI summary
According to one embodiment, a semiconductor device includes a first switch provided with a first electrode and a second electrode, a second switch provided with a third electrode and a fourth electrode, a first capacitor including a first wiring layer connected to the third electrode, a second wiring layer connected to the first electrode, and a first dielectric layer, a substrate, a third wiring layer connected to the first wiring layer and applied with a first voltage, a fourth wiring layer connected to the second wiring layer and applied with a second voltage, and a fifth wiring layer connected to the second and fourth electrodes, and applied with a third voltage. The first capacitor is arranged between the first and second switches. The third electrode faces the first electrode. The fourth electrode faces the second electrode and is connected to the second electrode in series.