Stacked Socket Interconnect Layout for Differential Crosstalk Cancelation
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Solution Overview
Problem
Existing approaches to mitigate differential crosstalk in semiconductor devices, such as reducing socket height and increasing ground pin count, lead to increased manufacturing challenges and costs, while also complicating the pin map and form factor.
Innovation Solution
Implementing a stacked structure with swapped vertical conductive pins and interconnects in a polarity swapped configuration to achieve differential crosstalk self-cancelation, reducing crosstalk by at least 20 dB at 20 GHz frequencies and optimizing PCIe channel speed scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If socket height is reduced to mitigate differential crosstalk, then crosstalk is reduced, but manufacturing complexity and cost increase
Solution Approach 1:
The patent inverts the traditional pin mapping approach by implementing polarity swapped configurations where adjacent differential pairs have opposite polarity assignments. Instead of reducing socket height to mitigate crosstalk, the invention swaps the polarity of pins in a stacked structure to achieve crosstalk self-cancelation, thereby maintaining standard socket heights while reducing manufacturing complexity
Solution Approach 2:
The patent converts the harmful effect of crosstalk into a beneficial self-cancelation mechanism. By carefully arranging differential pairs with swapped polarity in the stacked structure, the crosstalk signals from adjacent pairs interfere destructively, transforming the harmful crosstalk into a benefit that reduces overall interference without requiring height reduction
2Object-affected harmful factors
If ground pin count is increased to mitigate differential crosstalk, then isolation is improved, but pin count and form factor increase
Solution Approach 1:
The patent implements a self-service mechanism where the differential pairs themselves provide isolation through their swapped polarity configuration. Instead of relying on additional ground pins for isolation, the differential signals self-isolate through destructive interference, eliminating the need to increase pin count while maintaining effective isolation
Solution Approach 2:
The invention converts the potentially harmful crosstalk into a beneficial isolation mechanism. By arranging differential pairs with opposite polarity in the stacked structure, the crosstalk from adjacent pairs cancels itself out, providing effective isolation without requiring additional ground pins or increasing the overall pin count
3Object-affected harmful factors
If socket height is reduced to mitigate differential crosstalk, then crosstalk is reduced, but mechanical solution space is compressed
Solution Approach 1:
The patent inverts the approach by maintaining standard socket heights and instead inverting the polarity configuration of pins in the stacked structure. This allows the mechanical solution space to remain open and adaptable while achieving crosstalk reduction through electrical configuration rather than mechanical compression
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces crosstalk and optimizes speed scaling in high-speed channels without increasing the number of pins or socket height, thereby addressing the technical challenges and costs associated with existing methods.
Implementation Method 1
stacked structures having swapped vertical conductive pins and interconnects used for differential crosstalk self-cancelation
Data Source
AI summary
Embodiments include assemblies. An assembly includes a substrate having a first interconnect and a second interconnect. The first interconnect has a first conductive pad and a second conductive pad, and the second interconnect has a third conductive pad and a fourth conductive pad. The assembly includes a socket over the substrate. The socket has a first pin, a second pin, and a base layer with a first pad and a second pad. The first and second pins are vertically over the respective first and second interconnects. The first pad is directly coupled to the first pin and fourth conductive pad, while the second pad is directly coupled to the second pin and second conductive pad. The first pad is positioned partially within a footprint of the third conductive pad, and the second pad is positioned partially within a footprint of the first conductive pad.