Stacked SOI Shunt Switch Biasing for Lower Resistor Area
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Solution Overview
Problem
Existing stacked shunt switch designs require high-value resistors for biasing, leading to significant area penalties due to the need for numerous large resistors as the switch is split into segments, which complicates even RF signal distribution and switching time requirements.
Innovation Solution
A serial stacked shunt semiconductor on insulator (SOI) switch topology that distributes drain-source voltage across FET devices in the off state, allowing for the use of smaller valued resistors and reducing off-state loading, thereby minimizing the area required for bias resistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the switch is split into N segments with high-value resistors for biasing, then even RF signal distribution across transistors is achieved, but the area required for resistors increases significantly
Solution Approach 1:
The patent divides the stacked switch into multiple segments (N segments) and applies segmentation to the biasing resistors by connecting them in series. This allows the total resistance value to be distributed across multiple smaller resistor components, achieving the required high total resistance while reducing the area each individual resistor occupies.
Solution Approach 2:
The patent transitions from using a small number of high-value resistors to using multiple lower-value resistors connected in series. This dimensional change in the resistor configuration (from parallel/high-value to series/lower-value) reduces the area penalty while maintaining the necessary biasing function and RF signal distribution characteristics.
2Loss of time
If high-value resistors are used for biasing in stacked switches, then switching time requirements are met, but the number of high-value resistors increases leading to area penalties
Solution Approach 1:
The biasing resistor network is segmented into multiple series-connected resistors. This segmentation allows the total resistance to be achieved using multiple smaller resistor units, reducing the quantity of high-value resistors needed while maintaining the switching time performance through proper resistance value distribution.
Solution Approach 2:
The patent uses multiple resistors in series where each resistor has a lower individual value than the single high-value resistor it replaces. The cumulative effect of multiple partial resistance contributions achieves the total required resistance for meeting switching time requirements while reducing the number of high-value components.
3Strength
If the number of stacked devices exceeds 10, then the switch can handle higher voltages, but the requirement for very high value resistors leads to significant area penalties
Solution Approach 1:
For stacked switches with more than 10 devices requiring very high voltage handling capability, the patent segments the biasing resistance into multiple series-connected resistors. This allows achieving the necessary total resistance value for proper biasing without requiring a small number of extremely high-value resistors that would occupy excessive area.
Solution Approach 2:
The patent changes the resistor configuration from using fewer high-value resistors to using multiple lower-value resistors in series. This dimensional change in the resistance network architecture enables high voltage handling capability while minimizing the total area occupied by the biasing resistor network.
Data Source
AI summary
The described FET switch topology greatly reduces the off state loading experienced by the gate biasing resistors in a stacked FET structure. The FET switch topology evenly distributes the voltage across the FET switch topology which reduces the voltage across the gate biasing resistors when the stacked FET structure is in an off state. Because the off state loading is reduced, there is a corresponding reduction of the current through bias resistors, which permits a reduction in the size of the bias resistors. This permits a substantial reduction in the area attributed to the bias resistors in an integrated solution.