Stacked Solder Bumps with Intermediate Metal Layer for Thermal Reliability

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Solution Overview

Problem

Existing semiconductor devices face challenges in achieving reliable and stable electrical interconnections due to limitations in the fabrication of multi-bump structural electrical interconnections, which affect mechanical and thermal reliability and assembly processes.

Innovation Solution

A method involving the formation of a solder stack with at least two solder layers and an intermediate layer, where the solder layers are reflowed to create stacked solder bumps, with the intermediate layer having a higher melting point than the solder bumps, enhancing electrical connectivity and mechanical stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single solder layer is used for electrical interconnection, then the fabrication process is simple, but the mechanical and thermal reliability is insufficient

Engineering Contradiction:
Improvemechanical and thermal reliabilityVSAvoidmulti-bump structural complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The solder interconnection is divided into multiple discrete solder bumps stacked vertically, with each bump formed from a separate solder layer. This segmentation allows each layer to contribute to different aspects of reliability while maintaining fabrication simplicity through sequential processing

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple solder bumps are stacked one on top of another in a nested configuration, with each subsequent bump positioned on top of the previous one. This nesting approach achieves complex three-dimensional interconnections while using a systematic, repeatable fabrication process

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If solder layers are stacked to form multi-bump structure, then electrical connectivity is improved, but deformation and fracture occur during reflow

Engineering Contradiction:
Improveelectrical connectivityVSAvoidresistance to deformation and fracture
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

A barrier metal layer with higher melting point is introduced as an intermediary between the solder bumps. This intermediate layer acts as a structural support during reflow processing, preventing deformation and fracture of the solder layers while allowing proper electrical connectivity to be established

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The melting point parameter of the intermediate barrier layer is specifically chosen to be higher than that of the solder layers. This parameter change ensures that the barrier layer remains solid and structurally stable during the reflow process, providing mechanical support to prevent solder deformation

Inventive Principle:
Principle #35Parameter changes

3Reliability

If intermediate layer with higher melting point is added, then thermal reliability is improved, but fabrication complexity increases

Engineering Contradiction:
Improvethermal reliabilityVSAvoidfabrication process simplicity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The barrier metal layer is combined with the existing solder bump fabrication process by forming it as part of the same stacked structure. The barrier layer is deposited and patterned together with the solder layers in a unified fabrication sequence, avoiding separate manufacturing steps

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enables improved mechanical and thermal reliability, fine pitch assembly, and high thermal performance by forming a bump stack with a metal layer interposed between solder bumps, reducing deformation and fracture, and allowing for flexible gap control between the semiconductor device and package substrate.

Implementation Method 1

reflowing the solder stack to form a bump stack that is electrically connected to the chip pad

Methodology Applied
Scientific EffectReflow: Melting

Implementation Method 2

The metal layer may have a melting point greater than the first and second solder bumps

Methodology Applied
Scientific EffectThermal resistance: Heat Sink

Implementation Method 3

forming a first solder layer, the intermediate layer and a second solder layer which are stacked one atop the other

Methodology Applied
Scientific EffectElectroplating: Electroplating

Data Source

PatentUS9142498B2Semiconductor devices having stacked solder bumps with intervening metal layers to provide electrical interconnections
Publication Date: 2015.09.22 SAMSUNG ELECTRONICS CO LTD
  • US9142498B2 patent drawing
  • US9142498B2 patent drawing
  • US9142498B2 patent drawing

AI summary

An electrical interconnection can be provided using a bump stack including at least two solder bumps which are stacked on one another and at least one intermediate layer interposed between the at least stacked two solder bumps.