Stacked Solid Electrolytic Capacitor ESR Reduction
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Solution Overview
Problem
Conventional stacked solid electrolytic capacitors fail to effectively reduce equivalent series resistance (ESR) as the number of stacked layers increases, limiting the advantages of stacking in achieving lower impedance and higher capacitance.
Innovation Solution
A stacked solid electrolytic capacitor design featuring a conductive layer formed on the side faces of the capacitor elements, connecting cathode and anode sections through conductive paste, and using a conductive layer with a conductive polymer or inorganic oxide, which reduces ESR and equivalent series inductance (ESL) by enhancing parallel connection efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of stacked layers is increased to reduce ESR according to formula (1), then ESR should decrease, but in conventional stacked solid electrolytic capacitors the ESR reduction cannot be realized due to interface resistance and connection issues
Solution Approach 1:
The patent merges the cathode layers of multiple stacked solid electrolytic capacitor elements by forming a conductive layer that extends in the stacking direction on the side faces, electrically connecting the cathode layers in parallel. This merging approach enables the ESR reduction predicted by formula (1) by creating effective parallel connections between multiple capacitor elements, resolving the issue where conventional stacking failed to achieve the expected ESR reduction due to connection problems.
2Quantity of substance
If multiple stacked ceramic capacitors are connected in parallel to achieve lower impedance and smaller profile, then capacitance increases, but thermal resistance increases and the solution becomes complex
Solution Approach 1:
The patent combines multiple solid electrolytic capacitor elements into a single stacked structure with integrated conductive connections. By merging the cathode layers through the conductive layer formed on side faces and connecting anode sections, the patent creates a unified capacitor that achieves the combined capacitance of multiple elements while maintaining a compact profile and reducing thermal resistance compared to separate parallel-connected capacitors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design significantly reduces ESR and ESL, allowing for increased capacitance and lower impedance even with a greater number of stacked layers, effectively addressing the limitations of conventional methods.
Implementation Method 1
a conductive layer extending in the stacking direction is formed on at least part of a side face of an area where the cathode layers of the solid electrolytic capacitor elements are formed
Implementation Method 2
an anode formed of a valve action metal
Implementation Method 3
a dielectric formed on the surface of the valve action metal and comprising an oxide of the valve action metal
Data Source
AI summary
A stacked solid electrolytic capacitor includes a plurality of stacked solid electrolytic capacitor elements. Each solid electrolytic capacitor element includes an anode formed of a valve action metal, an anode section formed on an end of the anode, a dielectric formed on the surface of the valve action metal and including an oxide of the valve action metal, and a cathode layer formed on the dielectric. The cathode layers and the anode sections of the solid electrolytic capacitor elements are, respectively, connected to each other across the plurality of stacked solid electrolytic capacitor elements. A conductive layer extending in the stacking direction is formed on at least part of a side face of an area where the cathode layers of the solid electrolytic capacitor elements are formed.