Stacked Multi-Gate Source/Drain Isolation Using PEALD Insulating Layer

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Solution Overview

Problem

Existing isolation structures between source/drain features in stacked complementary field effect transistors (C-FETs) are not satisfactory, leading to electrical shorts and damage to channel layers during fabrication, particularly due to the pre-clean process affecting the interlayer dielectric layer.

Innovation Solution

A method involving a plasma-enhanced atomic layer deposition (PEALD) process to form an insulating layer with a greater deposition thickness and quality on the contact etch stop layer and interlayer dielectric layer, allowing for selective removal of the vertical portion without damaging the channel layers, thereby enhancing electrical isolation between top and bottom source/drain features.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If existing isolation structures (contact etch stop layer and interlayer dielectric layer) are used between source/drain features, then device density is improved, but electrical shorts occur and channel layers are damaged during fabrication

Engineering Contradiction:
Improvedevice densityVSAvoidelectrical isolation
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The isolation structure is segmented into multiple functional layers: contact etch stop layer, interlayer dielectric layer, and insulating layer. Each layer performs a specific function - the contact etch stop layer prevents etching of underlying layers, the interlayer dielectric provides base isolation, and the insulating layer (formed by PEALD) provides enhanced electrical isolation between source/drain features, preventing electrical shorts while maintaining device density

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The insulating layer acts as an intermediary between the interlayer dielectric layer and the source/drain features. This intermediate layer specifically addresses the electrical isolation problem by providing an additional barrier that prevents charge leakage and electrical shorts, while the contact etch stop layer serves as an intermediary protective layer during fabrication processes

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If pre-clean process is applied to remove contaminants, then cleaning effectiveness is improved, but interlayer dielectric layer is damaged

Engineering Contradiction:
Improvecleaning effectivenessVSAvoidinterlayer dielectric layer integrity
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The contact etch stop layer and insulating layer are deposited beforehand to cushion and protect the interlayer dielectric layer during subsequent pre-clean processes. These protective layers absorb the harsh cleaning conditions, preventing damage to the underlying interlayer dielectric layer while still allowing effective contaminant removal

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The contact etch stop layer and insulating layer are formed as preliminary protective structures before the pre-clean process. This preliminary action ensures that when aggressive cleaning is performed to remove contaminants, the interlayer dielectric layer is already protected and will not be damaged

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively improves electrical isolation and reliability of stacked multi-gate devices by preventing electrical shorts and maintaining the integrity of the channel layers, enhancing the overall performance and reliability of the semiconductor device.

Implementation Method 1

A method involving a plasma-enhanced atomic layer deposition (PEALD) process to form an insulating layer with a greater deposition thickness and quality on the contact etch stop layer and interlayer dielectric layer

Methodology Applied
Scientific EffectPlasma-enhanced atomic layer deposition: Plasma Enhanced Chemical Vapour Deposition

Data Source

PatentUS20240413220A1Stacked multi-gate device with an insulating layer between top and bottom source/drain features
Publication Date: 2024.12.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240413220A1 patent drawing
  • US20240413220A1 patent drawing
  • US20240413220A1 patent drawing

AI summary

Semiconductor structures and methods of forming the same are provided. An exemplary method includes depositing a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer over a bottom epitaxial source/drain feature formed in a bottom portion of a source/drain trench, etching back the CESL and the ILD layer to expose a top portion of the source/drain trench, performing a plasma-enhanced atomic layer deposition process (PEALD) to form an insulating layer over the source/drain trench, where the insulating layer comprises a non-uniform deposition thickness and comprises a first portion in direct contact with the ILD layer and a second portion extending along a sidewall surface of the top portion of the source/drain trench. Method also includes removing the second portion of the insulating layer and forming a top bottom epitaxial source/drain feature on the second portion of the insulating layer and in the source/drain trench.