3D-Stacked SPAD Die Layout for Higher Fill Factor
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Solution Overview
Problem
Current semiconductor devices with SPAD arrays face challenges in achieving high integration and effective area utilization due to limited size reduction by SPADs and waste of area in SPAD wafers.
Innovation Solution
A semiconductor device is fabricated by bonding a SPAD wafer with SPAD arrays, a TDC wafer with TDC arrays, and a logic wafer with peripheral logic circuits in a multi-wafer stacking technique, ensuring the SPAD arrays are directly bonded to the TDC arrays, maximizing integration and minimizing waste.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of SPADs or peripheral circuitry is reduced to improve integration density, then integration density improves, but detection performance deteriorates due to lower limit constraints from dark counting
Solution Approach 1:
The patent divides the semiconductor device into three separate wafers: SPAD wafer containing only photon detection elements, TDC wafer containing only timing conversion circuits, and logic wafer containing peripheral logic circuits. This segmentation allows each component to be optimized independently - SPADs maintain their detection performance while circuitry achieves high integration density on separate substrates.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional stacked architecture by bonding multiple wafers together. This vertical stacking enables high integration density without reducing the area of individual SPAD elements, effectively moving the integration solution from the two-dimensional plane to the third dimension.
2Reliability
If the area of SPAD arrays is increased to improve photon detection efficiency, then detection efficiency improves, but device area increases reducing integration density
Solution Approach 1:
By stacking SPAD, TDC, and logic circuits on separate wafers in the vertical dimension, the patent enables large-area SPAD arrays to achieve high photon detection efficiency while maintaining high integration density through the third dimension. The vertical stacking compactly packs what would otherwise require large horizontal space.
Solution Approach 2:
Separating SPAD arrays from circuitry onto different wafers allows the SPAD area to be maximized for photon detection without being constrained by circuit layout requirements, achieving both high detection efficiency and high integration density simultaneously.
3Device complexity
If peripheral circuits are integrated on the same wafer as SPAD arrays, then device complexity is reduced, but area utilization deteriorates due to waste of SPAD wafer area
Solution Approach 1:
The patent segments the device into functionally independent wafers, placing peripheral circuits on a separate logic wafer from the SPAD arrays. This eliminates area waste on the SPAD wafer while maintaining manageable device complexity through modular architecture.
Solution Approach 2:
By moving peripheral circuits to a separate wafer in the vertical stacking architecture, the patent achieves complete area utilization of the SPAD wafer for photon detection, while the logic wafer efficiently packs circuitry without interfering with SPAD array layout.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases the integration of SPAD arrays, enhancing the fill factor and photon detection efficiency of the semiconductor device, thereby improving the detection performance of single-photon detectors.
Implementation Method 1
capable of detecting single photons, which then liberate carriers due to the internal photoelectric effect
Implementation Method 2
A single-photon avalanche diode (SPAD) is a Geiger-mode (operating at a voltage higher than the breakdown voltage) avalanche photodiode
Data Source
AI summary
A semiconductor device and a semiconductor die are disclosed. The semiconductor device includes: a SPAD wafer containing SPAD dies formed thereon with respective SPAD arrays; a TDC wafer containing TDC dies formed thereon with respective TDC arrays; and a logic wafer containing logic dies formed thereon with respective peripheral logic circuits. The SPAD wafer, TDC wafer and logic wafer are bonded in the sequence set forth. The TDC arrays and peripheral logic circuits are arranged on the TDC and logic wafers, respectively, and the SPAD arrays are bonded to the TDC arrays. The three wafers are bonded and integrated together to form the semiconductor device using a multi-wafer stacking technique. The increased integration of the semiconductor device means an increased fill factor of SPAD arrays for same size, resulting in improved photon detection efficiency of the semiconductor device and improved detection performance of single-photon detectors fabricated from the semiconductor device.