Stacked SPAD Pixel Architecture for In-Pixel Quenching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional imaging systems with single-photon avalanche diodes (SPADs) face challenges in achieving active pixel quenching and minimizing package size while ensuring reliable connections, particularly when SPADs and high voltage switches are formed on separate chips or packages.
Innovation Solution
The implementation of a stacked die arrangement, where SPAD pixels are vertically stacked with analog high voltage transistors and digital readout logic, utilizing through-silicon vias and interconnect stacks to form a compact and reliable imaging system, enabling active in-pixel quenching and reducing the overall package footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If SPADs and high voltage switches are formed on separate chips or packages, then manufacturing flexibility is improved, but connection reliability deteriorates and package size increases
Solution Approach 1:
The patent merges SPAD pixels, high voltage switches, and readout logic onto a single integrated circuit chip. This integration eliminates the need for external wire bonding and packaging connections between separate components, thereby improving connection reliability while maintaining manufacturing flexibility through monolithic fabrication processes.
Solution Approach 2:
The patent implements a three-dimensional stacked die architecture where sensor die containing SPADs are vertically stacked with analog high voltage die and digital readout logic die. Through-silicon vias (TSVs) provide vertical interconnections between stacked layers, enabling compact integration that improves connection reliability while reducing package footprint compared to planar arrangements.
2Adaptability or versatility
If SPADs and high voltage switches are formed on separate chips or packages, then design adaptability is improved, but package size increases
Solution Approach 1:
The patent transitions from a two-dimensional planar layout to a three-dimensional stacked die architecture. By stacking sensor die, analog high voltage die, and digital readout logic die vertically and using through-silicon vias for interconnections, the patent achieves compact integration that dramatically reduces package footprint while maintaining design adaptability through modular die stacking configurations.
3Measurement precision
If active pixel quenching is implemented in conventional configurations, then detection performance is improved, but package complexity increases
Solution Approach 1:
The patent integrates high voltage switches, quenching circuitry, and readout logic directly on the same chip as the SPAD pixels in a monolithic configuration. This integration simplifies the overall package structure by eliminating external quenching circuitry and interconnections, while maintaining active pixel quenching functionality for improved detection performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for improved reliability and a smaller form factor, enhancing the detection rate of incident light and reducing the need for wire bonding, resulting in a more efficient and compact imaging system.
Implementation Method 1
at least some of the second TSV structures can be coupled to routing structures in the sensor die and to routing structures in the digital die
Implementation Method 2
A SPAD is a type of P-N junction diode biased above a breakdown voltage using a high voltage. In this state, the SPAD can be sensitive to a single impinging photon
Data Source
AI summary
Circuitry is provided that includes a first die, a second die, and a third die that are vertically stacked. The second die may have a front side facing the third die and a back side facing the first die. The first die can include a plurality of single-photon avalanche diodes (SPADs). The second die can include a plurality of switches coupled to cathode terminals of the plurality of SPADs in the first die. The third die can include digital readout logic coupled to the plurality of switches in the second die. The plurality of switches in the second die can be power using a high voltage and are sometimes referred to as analog high voltage switches. The digital readout logic in the third die can be power using a voltage that is lower than the high voltage being used to power the second die.