Stacked SPI Flash Memory Die with Die Select Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing flash memory devices with stacked SPI flash memory die face challenges in managing multiple chip select signals, leading to increased manufacturing costs and limitations in implementing Quad SPI in 8-pin packages, while also lacking efficient concurrent operation capabilities.
Innovation Solution
A flash memory device with a stacked arrangement of two SPI flash memory dies, where each die has a unique identifier and set of SPI-compliant pins, allowing for parallel coupling and concurrent operation management through a Die Select instruction to enable specific dies to respond to SPI or Universal instruction sets, thereby simplifying chip select signal management and enabling Quad SPI in an 8-pin package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple chip select signals are used for stacked SPI flash memory die, then each die can be independently controlled, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent implements a universal chip select mechanism where a single /CS pin controls multiple stacked dies. The Die Select instruction enables the controller to address specific dies within the stack through software-based die identification and selection, rather than requiring separate physical chip select lines for each die. This multi-functional approach allows one pin to serve the chip select function for the entire stack while internal logic routes commands to the appropriate die.
2Reliability
If two pins are dedicated for chip select in an 8-pin package, then multiple stacked dies can be controlled, but Quad SPI interface is eliminated
Solution Approach 1:
The patent merges the chip select functionality for multiple dies into a single physical pin. By combining the /CS signals and using a unified chip select line that works in conjunction with Die Select instructions, the design consolidates what would traditionally require separate pins into one shared resource, thereby freeing up package pins for Quad SPI operations.
Solution Approach 2:
The Die Select instruction acts as an intermediary mechanism between the single /CS pin and multiple stacked dies. This software-based die selection protocol mediates the connection between the controller and individual dies, enabling precise die addressing without requiring separate physical chip select lines for each die in the stack.
3Quantity of substance
If stacked SPI flash memory die are used to achieve higher density, then capacity increases, but the ability to execute concurrent operations is limited
Solution Approach 1:
The patent segments the stacked dies into independently addressable units through the Die Select instruction mechanism. Each die can be individually selected and operated upon by the controller, allowing concurrent read operations from different dies or concurrent execution of read and erase operations across different dies, thereby improving overall system productivity while maintaining high capacity.
Data Source
AI summary
Any number of Serial Peripheral Interface (“SPI”) flash memory die may be stacked and packaged using any desired multi-chip packaging technique to realize any one or combination of various capabilities such as low per-bit cost, high density storage, code shadowing to RAM, and fast random access for “execute in place” applications, while preserving the advantages of the SPI interface. During device manufacture, each of the stacked die is assigned a unique identifier or “Die ID” relative to the other stacked die in the package. During normal operations, the unique Die IDs are used by a Die Select instruction to enable one of the stacked die to respond to subsequent instructions on the SPI interface, while disabling the other stacked die in the package from responding to subsequent instructions but for certain “Universal” instructions which include the Die Select instruction. Concurrent operations by the stacked die are supported.