Stacked Spiral Inductor Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
Conventional stacked spiral inductors suffer from high parasitic capacitance between metal layers and between the metal layers and the silicon substrate, which negatively impacts their performance, especially at high frequencies.
Innovation Solution
The design includes multiple stacked insulating and inductive metal layers with conductive coils of varying sizes, where each lower coil is retracted towards the center relative to the upper coil, and a patterned ground shield to reduce parasitic capacitance and electromagnetic interference, while maintaining the same substrate area and process technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the planar spiral inductors in adjacent metal layers are designed with the same shape and size, then the manufacturing process is simplified, but the parasitic capacitance between metal layers increases significantly
Solution Approach 1:
The patent applies asymmetry by designing the planar spiral inductors in adjacent metal layers with different shapes and sizes. Specifically, the first planar spiral inductor in the first metal layer and the second planar spiral inductor in the second metal layer are designed to have different geometries, which reduces the parasitic capacitance between the metal layers while still allowing for simplified manufacturing through standard photolithography processes.
2Area of stationary object
If conventional stacked spiral inductor design is used, then the substrate area is utilized, but the parasitic coupling capacitance between metal layer and silicon substrate becomes too large
Solution Approach 1:
The patent introduces an intermediary element - the patterned ground shield - positioned between the metal layers and the silicon substrate. This ground shield acts as a mediator that reduces the parasitic coupling capacitance between the planar spiral inductors and the substrate, while still utilizing the substrate area effectively for the inductor structure.
3Ease of manufacture
If the existing process technology is not changed, then manufacturing compatibility is maintained, but the parasitic capacitance cannot be reduced
Solution Approach 1:
The patent applies parameter changes by modifying the geometric parameters of the planar spiral inductors - specifically using different shapes and sizes for inductors in adjacent metal layers - while maintaining compatibility with existing manufacturing processes. This allows parasitic capacitance reduction through design parameter optimization rather than process technology changes.
Data Source
AI summary
A stacked spiral inductor, comprising: a substrate, and multiple stacked insulating layers and inductive metal layers formed on the substrate by means of a semiconductor process. Each inductive metal layer comprises a conductive coil in a shape of a spiral and a through hole area used for connecting two adjacent inductive metal layers. The conductive coils of the inductive metal layers have a common coil center. In two adjacent inductive metal layers, the conductive coil of the lower inductive metal layer is retracted toward the coil center with respect to the conductive coil of the upper inductive metal layer.