Stacked SRAM Layout for Dense 3D IC Interconnects
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Solution Overview
Problem
Conventional 3D IC fabrication methods face limitations in interconnection density and manufacturing cost due to large Through Silicon Vias and complex sequential processing, while existing 3D Nanofabric designs impose layout constraints that limit flexibility and scalability.
Innovation Solution
A 3D IC design with vertically stacked SRAM circuits featuring identical layouts and a single routing layer, where bit lines are horizontally routed and pull-up and pull-down voltage rails are vertically shared, allowing for area-efficient and cost-effective manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If Through Silicon Vias (TSVs) are used for interconnection in parallel 3D integration, then stacking of several circuits is enabled, but the large footprint of TSVs limits the interconnection density and results in significant area overhead
Solution Approach 1:
The patent transitions from planar 2D interconnection to 3D vertical interconnection by stacking multiple device tiers vertically. The bit cells are arranged in multiple tiers along the vertical direction, with word lines extending vertically through the stacked tiers to connect bit cells across different levels, thereby achieving high-density interconnection without large area overhead.
Solution Approach 2:
The patent implements a hierarchical nesting structure where multiple device tiers are stacked vertically, each containing SRAM circuits with bit cells. The word lines nest through multiple tiers simultaneously, and bit cells within each tier are arranged in rows and columns, creating a nested multi-level architecture that maximizes interconnection density.
2Length of moving object
If sequential 3D integration is used with conventional vias, then smaller vertical interconnect pitches are enabled, but the number of stacked vertical tiers is limited by the cost and complexity of the manufacturing process
Solution Approach 1:
The patent segments the SRAM circuit into functionally independent components: bit cells, word lines, and bit lines. The bit cells are segmented into multiple tiers, while word lines serve as shared vertical interconnects across all tiers. This segmentation allows each tier to be processed independently yet interconnected through the shared word line structure, reducing manufacturing complexity.
Solution Approach 2:
The word lines serve multiple functions simultaneously: they act as select signals for bit cells within their own tier, serve as vertical interconnects connecting bit cells across different tiers, and provide a common routing structure for all stacked device tiers. This multi-functionality reduces the number of dedicated interconnect structures needed, simplifying the manufacturing process.
3Ease of manufacture
If 3D Nanofabric design with identical layouts is used, then manufacturing costs are reduced and parallel processing is enabled, but the layout constraints limit design flexibility
Solution Approach 1:
The patent applies identical layout patterns to the bit cell cores across all device tiers to enable parallel processing and reduce manufacturing costs. However, the peripheral circuits and interconnection structures (such as word line connections and bit line routing) are allowed to vary locally to meet specific design requirements, thereby maintaining layout flexibility despite the standardized core design.
Data Source
AI summary
The disclosed 3D IC includes a plurality of vertically stacked device tiers, each device tier comprising an SRAM circuit, each SRAM circuit comprising an SRAM bit cell, wherein the bit cells are stacked on top of each other to define a stack of bit cells and wherein and each bit cell comprises first and second pass transistors, first pull-up and pull-down transistors, and second pull-up and pull-down transistors. The SRAM circuits have an identical layout and each SRAM circuit comprises: a single active layer forming an active semiconductor pattern of the transistors of the bit cell, and a single routing layer of horizontally routed conductive lines comprising a complementary pair of first and second bit lines connected to the bit cell of the SRAM circuit, gate lines defining gates of the transistors of the bit cell of the SRAM circuit, and wiring lines forming interconnections of the bit cell of the SRAM circuit.