Stacked Load-less SRAM Cell Design for High Integration
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Solution Overview
Problem
Bulk CMOS SRAM cells have a low degree of integration and poor latch-up immunity due to the arrangement of transistors in a plane on a substrate, leading to increased cell size and stability issues.
Innovation Solution
A stacked load-less SRAM device is designed by stacking a pair of transmission transistors on a pair of driving transistors, with specific electrical connections and insulating films to reduce cell size and improve integration, using a semiconductor substrate with active regions and overlapping semiconductor layers to facilitate efficient signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If transistors are arranged in a plane on a substrate, then device structure is simple, but cell size increases and degree of integration decreases
Solution Approach 1:
The patent transitions from planar (2D) transistor arrangement to stacked (3D) arrangement, where transmission transistors are positioned vertically above driving transistors. This dimensional change enables higher integration density without increasing the planar footprint of the memory cell, directly resolving the contradiction between structural simplicity and cell size reduction.
2Ease of manufacture
If transistors are arranged in a plane on a substrate, then manufacturing process is simple, but latch-up immunity deteriorates
Solution Approach 1:
By stacking transmission transistors above driving transistors in the vertical dimension, the patent increases spacing between transistor components in the planar direction. This spatial separation in 3D architecture improves latch-up immunity by reducing parasitic coupling while maintaining compatibility with standard CMOS manufacturing processes.
3Productivity
If cell size is reduced by stacking transistors, then degree of integration improves, but device complexity increases
Solution Approach 1:
The stacked configuration achieves higher integration by utilizing the vertical dimension, allowing multiple transistor layers within a single memory cell footprint. This approach increases the number of transistors per unit area without requiring complex interconnect routing, as vertical connections are achieved through direct stacking rather than lateral wiring.
Solution Approach 2:
The shared source/drain regions between stacked transistors serve multiple functions simultaneously, reducing the total number of discrete components needed. The common diffusion regions act as both source/drain for driving transistors and as part of the transmission transistor structure, simplifying the overall device architecture despite the increased transistor count.
Data Source
AI summary
In a stacked load-less static random access memory (SRAM) device in which a pair of transmission transistors is stacked on a pair of driving transistors, the stacked load-less SRAM device includes first and second transistors arranged in first and second active regions separately on a semiconductor substrate and third and fourth transistors arranged on first and second semiconductor layers over the first and second transistors. A first drain region of the first transistor, a third drain region of the third transistor, and a second gate of the second transistor are electrically connected through a first contact node. A second drain region of the second transistor, a fourth drain region of the fourth transistor, and a first gate of the first transistor are electrically connected through a second contact node.