Staggered Stacked SRAM FET Layout to Prevent Structural Collapse
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Solution Overview
Problem
As devices in nanosheet technology scale down, they interfere with each other, and stacking them to increase density leads to structural issues such as collapse due to increased height, necessitating a solution for independent fabrication and alignment to prevent these problems.
Innovation Solution
The solution involves fabricating a bottom transistor with a gate region aligned along a first axis and an upper transistor with a gate region aligned perpendicular to it, allowing for independent fabrication and attachment, which prevents the creation of high aspect ratio fins and allows for more flexible alignment and contact arrangements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If devices are stacked to increase device density, then device density is improved, but the combined height increases causing structural collapse
Solution Approach 1:
The patent transitions from planar device arrangement to three-dimensional stacked configuration, placing devices at different vertical levels (first device at first vertical level, second device at second vertical level). This dimensional change enables increased device density while maintaining structural stability through proper vertical spacing and alignment.
Solution Approach 2:
The patent divides the stacked structure into separate device units (first device and second device) that can be independently formed and then combined. Each device is formed on its own substrate and then attached to the other, allowing independent optimization of each device while maintaining overall structural integrity.
2Quantity of substance
If nanosheet technology is scaled down to increase device density, then device density is improved, but device interference increases causing functional issues
Solution Approach 1:
By arranging devices in vertical stacks rather than horizontal arrays, the patent reduces lateral device interference while maintaining high device density. The vertical separation between devices at different levels minimizes electromagnetic and physical interference compared to closely spaced lateral arrangements.
Solution Approach 2:
The patent employs asymmetric alignment between stacked devices, where the second device is offset relative to the first device along the channel direction. This asymmetric positioning reduces device interference by ensuring that not all components of adjacent devices are directly aligned, thereby minimizing parasitic interactions.
3Adaptability or versatility
If devices are aligned perpendicular to each other in stacked configuration, then fabrication flexibility is improved, but alignment precision requirements increase
Solution Approach 1:
The patent forms each device completely on its own substrate before attachment, including all device components such as channels, gates, and contacts. This preliminary formation allows each device to be independently optimized and reduces the complexity of simultaneous multi-device fabrication, while alignment markers are pre-formed to guide subsequent alignment.
Solution Approach 2:
The patent employs alignment markers (first alignment marker and second alignment marker) as intermediary reference structures that facilitate precise perpendicular alignment between stacked devices. These markers provide visual or automated alignment references that reduce the difficulty of achieving high precision perpendicular alignment during the attachment process.
Data Source
AI summary
A microelectronic structure including a bottom transistor having a gate region aligned along a first axis. An upper transistor located on top of the bottom transistor, where the upper transistor has a gate region that is aligned along a second axis, and where the second axis is perpendicular to the first axis.