Stacked SRAM Transistor Layout With Merged Through Contacts
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Solution Overview
Problem
There is a challenge in improving the integration density and reliability of static random access memory (SRAM) cells, particularly due to the arrangement of six transistors in a single SRAM cell, which hinders efficient packing and performance.
Innovation Solution
The implementation of merged through contacts that are electrically connected to lower, middle, and upper source/drain patterns, along with aligned middle and lower source/drain contacts, enhances the integration density of semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If six transistors are arranged in a single SRAM cell using conventional layout, then the SRAM cell can be formed with standard configuration, but the integration density is limited and packing efficiency is poor
Solution Approach 1:
The patent merges multiple source/drain contacts (lower, middle, and upper) into a single integrated contact structure that connects to multiple transistor regions simultaneously. This merging approach reduces the number of separate contact elements needed and improves space utilization within the SRAM cell, directly addressing the integration density challenge while managing the complexity of six-transistor configuration.
Solution Approach 2:
The patent introduces a vertical stacking dimension by implementing lower, middle, and upper source/drain patterns at different vertical levels. This three-dimensional arrangement allows multiple contacts to be positioned at different heights, enabling more efficient packing of the six transistors within the SRAM cell footprint and improving integration density without simply expanding the planar area.
2Quantity of substance
If multiple separate contacts are used for lower, middle, and upper source/drain patterns, then each contact can be independently configured, but the integration density decreases and device packing becomes less efficient
Solution Approach 1:
The patent combines multiple source/drain contacts into a merged through contact structure that vertically integrates connections to lower, middle, and upper source/drain patterns. This single merged contact performs the function of multiple separate contacts, improving integration density while the internal multi-level structure maintains the necessary electrical connectivity flexibility for manufacturing.
Solution Approach 2:
The merged through contact structure serves multiple functions simultaneously: it provides electrical connection to lower, middle, and upper source/drain patterns, acts as a vertical interconnect, and reduces the total contact count. This multi-functional design achieves high integration density without sacrificing the configurability needed for manufacturing different SRAM cell variations.
Data Source
AI summary
A semiconductor device may include, a substrate; a first lower sheet pattern on the substrate; a second lower sheet pattern on the substrate; a first lower gate electrode that extends around the first lower sheet pattern; a second lower gate electrode that extends around the second lower sheet pattern; a middle sheet pattern on the first lower sheet pattern; an upper sheet pattern on the middle sheet pattern; first and second lower source/drain patterns on opposite sides of the first lower sheet pattern; first and second middle source/drain patterns on opposite sides of the middle sheet pattern; first and second upper source/drain patterns on opposite sides of the upper sheet pattern; a merged through contact that extends in the second lower source/drain pattern, the second middle source/drain pattern, and the second upper source/drain pattern; and a lower gate contact electrically connected to the second lower gate electrode.