Stacked SRAM FET Gates With Oxygen Layers for Write Margin
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Solution Overview
Problem
In semiconductor device fabrication, particularly for SRAM devices with stacked FET structures, there is a challenge in effectively controlling the threshold voltage (Vt) to improve the write margin (WRM), as existing methods struggle to balance the performance of n-type and p-type FETs to prevent write failures due to noise voltages.
Innovation Solution
The implementation of an oxygen blocking layer on the metal gate of the pull-down transistors and an oxygen rich layer on the pass gate transistor, allowing for tuning of the threshold voltage by weakening the pull-up transistors and strengthening the pull-down transistors, thereby enhancing the write margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SRAM cells are used without threshold voltage tuning, then the device structure is simple, but the write margin is insufficient
Solution Approach 1:
The patent applies local quality by introducing oxygen blocking layers specifically on the metal gates of pull-up transistors and oxygen rich layers on pull-down transistors. This creates localized threshold voltage adjustments in specific regions of the SRAM cell, allowing differential tuning of transistor strengths without redesigning the entire device structure. The selective application of oxygen-related layers to specific transistor types enables precise control over write margin while maintaining overall structural simplicity.
2Reliability
If threshold voltage is tuned using oxygen blocking or rich layers, then the write margin improves, but the manufacturing process becomes more complex
Solution Approach 1:
The patent employs parameter changes by modifying the oxygen content and chemical composition of metal gate layers through controlled oxidation or oxygen blocking during fabrication. By adjusting oxidation conditions, layer thicknesses, and oxygen exposure parameters, the threshold voltage of transistors can be tuned to optimize write margin. This approach transforms a performance optimization problem into a controllable manufacturing parameter adjustment process.
3Area of stationary object
If stacked FET structure is implemented, then the area scaling is achieved, but the control of threshold voltage shift becomes more difficult
Solution Approach 1:
The patent applies segmentation by dividing the stacked FET structure into functionally distinct pull-up and pull-down transistor groups with different oxygen treatment. This segmentation allows independent threshold voltage control for each transistor type within the compact stacked architecture. By treating the metal gates of different transistor types differently with respect to oxygen exposure, the patent maintains individual control over threshold voltage shifts despite the vertically integrated space-saving structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively improves the write margin by adjusting the threshold voltages of n-type and p-type FET regions, reducing the risk of write failures and enhancing data storage reliability in SRAM devices.
Implementation Method 1
an oxygen blocking layer provided on the first metal gate
Implementation Method 2
an oxygen rich layer provided on the second metal gate
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a semiconductor device comprising: a first stacked field effect transistor (FET) structure in a first device area, the first stacked FET structure comprising a first pull down (PD) transistor, and a first pull up (PU) transistor disposed over the first PD transistor, a first metal gate that is shared by the first PD transistor and the first PU transistor; and an oxygen blocking layer provided on the first metal gate.