Stacked SRAM Cell Layout With Topside and Backside Routing
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Solution Overview
Problem
Current standard cell designs face challenges in providing adequate routing for both control signals and power signals to stacked transistors without increasing the size of the standard cell, especially when limited to topside routing.
Innovation Solution
Implementing routing in both topside and backside metal layers to connect control signals and power signals to vertically stacked transistors, allowing for compact standard cell constructions that adhere to current manufacturing constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If routing is provided only through topside metal layers, then the standard cell size can be kept compact, but adequate routing access to stacked transistors cannot be achieved
Solution Approach 1:
The patent introduces backside metal layers as a second routing dimension, allowing power and control signals to access stacked transistors from both topside and backside. This dimensional expansion enables adequate routing access without increasing the planar footprint of the standard cell, as routing paths are distributed across multiple layers rather than confined to a single plane.
2Productivity
If standard cell size is reduced, then circuit density increases, but routing access to components becomes more difficult
Solution Approach 1:
By utilizing backside metal layers in addition to topside routing, the patent enables high circuit density in reduced cell sizes while maintaining routing accessibility. The vertical stacking of transistors combined with multi-layer routing from both sides allows compact integration without sacrificing the ability to deliver power and control signals to all components.
Solution Approach 2:
The routing function is segmented across multiple metal layers (topside and backside), with different layers handling different signal types or routing paths. This segmentation allows efficient distribution of power and control signals to densely packed stacked transistors without requiring any single layer to carry all routing traffic, thus maintaining ease of operation at high density.
3Area of stationary object
If more transistors are stacked vertically, then area is reduced, but providing power and control signal routing becomes more complex
Solution Approach 1:
The patent resolves routing complexity in vertically stacked transistor configurations by introducing backside metal layers as an additional routing dimension. This allows power and control signals to reach transistors at different vertical levels through strategically placed vias and interconnects in both topside and backside layers, distributing the routing complexity across multiple dimensions rather than concentrating it in a single plane.
Data Source
AI summary
A SRAM cell layout that implements stacked transistors is disclosed. The cell layout utilizes both topside metal routing and backside metal routing along with stacked transistors to provide multiple transistors for implementation of inverters and pass gates in a memory cell. Various connection routes between components of the transistors (e.g., gates, sources, and drains) are made to allow cross-coupling between inverters in the memory cell.