Stacked SRAM Cell Layout With Shared Pads for Higher Density
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high integration density and improved electrical characteristics, particularly in SRAM cells, which are essential for meeting the increasing demands of the electronics industry for reliability and performance.
Innovation Solution
A semiconductor memory device is designed with a substrate featuring a 2x2 array of PMOSFETs and NMOSFETs in lower and upper active regions, respectively, with vertically stacked transistors and a unique metal layer and back-side metal layer configuration that includes shared pads and vias to enhance connectivity and reduce electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional planar transistor layouts are used, then manufacturing process is simpler, but integration density is low and cell area is large
Solution Approach 1:
The patent transitions from a two-dimensional planar layout to a three-dimensional stacked configuration by vertically stacking lower and upper active regions with multiple transistor layers. This vertical stacking enables higher integration density by utilizing the third dimension (depth) rather than only horizontal expansion, allowing more transistors to be packed into a smaller footprint area.
Solution Approach 2:
The patent implements nested structures by placing upper active regions containing transistors within and above the lower active regions. The lower bit line structures are nested below upper bit line structures, and source/drain regions are nested within channel regions across multiple layers. This nesting approach maximizes space utilization and increases integration density.
2Reliability
If conventional metal layer configurations are used, then manufacturing is simpler, but electrical resistance is high and connectivity is poor
Solution Approach 1:
The patent divides the metal interconnection system into multiple segmented layers including lower bit lines, upper bit lines, lower shared pads, and upper shared pads. Each metal layer is independently patterned and connected through vertical vias, allowing optimized electrical pathways and reduced resistance by distributing current across multiple segmented conductive paths rather than relying on single long traces.
Solution Approach 2:
The patent adds vertical dimension to the metal interconnection system by stacking lower and upper metal layers at different heights. This three-dimensional metal architecture reduces electrical resistance by providing multiple parallel conduction paths and shorter current paths compared to planar layouts, thereby improving electrical characteristics and signal integrity.
3Quantity of substance
If larger cell area is used, then transistor layout is simpler, but integration density decreases
Solution Approach 1:
The patent achieves high integration density by transitioning from lateral expansion to vertical stacking. Multiple transistor layers are stacked in the vertical direction, with lower transistors in the first active region and upper transistors in the second active region positioned above. This vertical arrangement dramatically reduces the horizontal footprint of each logic unit while maintaining functional complexity.
Solution Approach 2:
The patent merges multiple transistor functions into vertically stacked configurations where lower and upper transistors share common structures such as bit lines and source/drain regions. This merging approach consolidates what would otherwise require separate lateral spaces into compact vertical units, increasing the number of transistors per unit area.
Data Source
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AI summary
A semiconductor memory device includes a substrate including a first surface and a second surface, which are opposite to each other, a lower active region on the first surface, the lower active region including a lower gate electrode and a lower active contact, which are spaced apart from each other, an upper active region stacked on the lower active region, the upper active region including an upper gate electrode and an upper active contact, which are spaced apart from each other, a first metal layer on the first surface, and a back-side metal layer on the second surface. The back-side metal layer includes a first shared pad electrically connecting the lower gate electrode to the lower active contact. The first metal layer includes a second shared pad electrically connecting the upper gate electrode to the upper active contact.