Stacked SRAM Shared Wordlines for Higher Density Memory Layouts
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Solution Overview
Problem
Current SRAM devices face challenges in achieving higher density and lower cost, which are essential for improving processor performance and reducing costs in complex systems.
Innovation Solution
The solution involves stacking SRAM cells and connecting horizontal wordlines vertically, allowing for the same memory to be stored in half the area or doubling the memory in the same area, using shared wordlines to connect multiple SRAM cells, and implementing active cooling systems to operate at lower temperatures, thereby enhancing conductivity and reducing manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If SRAM cells are stacked vertically and wordlines are shared between layers, then storage density increases and area is reduced, but device complexity increases due to three-dimensional interconnect structures
Solution Approach 1:
The patent transitions from traditional planar SRAM organization to a three-dimensional stacked architecture where memory cells are arranged vertically across multiple layers. Wordlines and bitlines are extended into the third dimension with vertical interconnects (via structures) connecting corresponding lines between layers, enabling higher storage density without proportionally increasing lateral area.
Solution Approach 2:
The patent merges corresponding wordline segments from different stacked layers by connecting them through vertical interconnect structures. This allows a single wordline signal to simultaneously access multiple memory cells across different layers, effectively combining the functionality of separate wordlines into a unified interconnect system.
2Ease of manufacture
If wordlines are shared vertically between stacked SRAM layers, then manufacturing complexity is reduced, but signal integrity may deteriorate due to longer vertical connection paths
Solution Approach 1:
The patent segments the vertical wordline interconnect into discrete via structures that connect specific layers, rather than creating one continuous long vertical path. This segmentation allows for localized optimization of each interconnect segment and reduces the cumulative effect of resistance and capacitance along the entire vertical path.
Solution Approach 2:
The patent introduces intermediate connection points and redistribution layers that act as mediators between stacked SRAM layers. These intermediate structures provide signal regeneration points and allow for impedance matching, thereby maintaining signal integrity across the vertical interconnect path.
3Power
If active cooling systems are implemented to operate at lower temperatures, then conductivity increases and performance improves, but device complexity and cost increase
Solution Approach 1:
The patent implements self-service cooling where the SRAM device itself generates the cooling effect through controlled self-heating mechanisms or utilizes the natural thermal properties of the stacked structure. The three-dimensional arrangement provides enhanced heat dissipation pathways without requiring external active cooling systems.
Solution Approach 2:
The patent changes the operating temperature parameter by utilizing the inherent thermal characteristics of the stacked architecture. The vertical arrangement and material selection are optimized to maintain lower operating temperatures naturally, improving conductivity without adding complex active cooling infrastructure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster operation and increased storage capacity without increasing the length of wordlines or bitlines, leading to more efficient and cost-effective SRAM devices that can improve processor performance and reduce system complexity.
Implementation Method 1
a metallization structure electrically connecting a gate electrode of the first access transistor to a gate electrode of the second access transistor
Implementation Method 2
implementing active cooling systems to operate at lower temperatures, thereby enhancing conductivity
Implementation Method 3
active cooling systems to operate at lower temperatures
Data Source
AI summary
Stacked static random-access memory (SRAM) circuits have doubled word length for a given SRAM cell area. An integrated circuit (IC) die includes stacked SRAM cells in vertically adjacent device layers with access transistors connected to a common wordline. The IC die with stacked SRAM cells having a common word line may be attached to a substrate and coupled to a power supply and, advantageously, to an active-cooling structure. SRAM cells may be formed in vertically adjacent layers of a substrate and electrically connected at their access transistor gate electrodes.