Stacked SRAM Transistors with Common Gate for Area Reduction
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Solution Overview
Problem
Conventional SRAM technology faces challenges in achieving area-efficient circuit design due to the large surface area occupied by bit cells, despite advancements in miniaturization of transistors, as the layout and interconnection of transistors are not optimized for space efficiency.
Innovation Solution
The semiconductor device employs stacked complementary transistor pairs with a single common gate electrode for each pair, arranging gate electrodes on the same track to reduce surface area, and uses cross-couple contacts to interconnect drains without relying on higher-level interconnections, allowing for a more compact design by utilizing vertical dimensions and short gate electrodes to minimize capacitive coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional transistor layout and interconnection methods are used, then transistor functionality is achieved, but the surface area occupied by bit cells becomes large
Solution Approach 1:
The patent transitions from planar transistor layout to a vertical stacked configuration where transistors are arranged in multiple levels above the substrate. The gate electrodes extend in the vertical direction (z-axis) to control channels at different heights, enabling three-dimensional space utilization and significantly reducing the footprint area occupied by each bit cell while maintaining transistor functionality.
Solution Approach 2:
The patent combines multiple transistor functions into a compact stacked structure where complementary transistor pairs share common substrate regions and are vertically integrated. The gate electrodes are arranged to control multiple channels simultaneously, merging spatial separation with functional integration to achieve higher density without sacrificing circuit performance.
2Area of stationary object
If transistor miniaturization is pursued, then transistor size decreases, but layout and interconnection optimization is required to achieve area-efficient circuitry
Solution Approach 1:
The patent segments the bit cell into distinct vertical layers with each transistor pair occupying a specific height range. The gate electrodes are segmented into multiple sections (e.g., gate electrode 130 with first and second sections, gate electrode 230 with first and second sections) that control different channels at different vertical positions, allowing independent optimization of each segment while maintaining overall compactness.
Solution Approach 2:
The patent resolves layout complexity by moving from two-dimensional planar arrangement to three-dimensional vertical stacking. The gate electrodes extend vertically to control channels at different heights, and cross-couple contacts are positioned at specific vertical levels to interconnect transistor drains. This vertical dimensionality change simplifies the interconnection scheme by reducing the need for complex lateral routing while achieving area-efficient circuitry.
Data Source
Figure 1a
Figure 1b~1c
Figure 2
AI summary
According to an inventive aspect there is provided a semiconductor device comprising: first and second sets of transistors (100, 200) comprising a pass transistor (110, 210) and a stacked complementary transistor pair (120, 220) of a lower transistor (122, 222) and an upper transistor (124, 224), wherein first transistor comprises a semiconductor channel (110c, 122c, 124c) extending along a horizontal first fin track, and each second transistor comprises a semiconductor channel extending along a separate second fin track parallel to the first fin track, and wherein the semiconductor channels of the pass transistors and of the lower transistors are arranged at a first level and the semiconductor channels of said upper transistors are arranged at a second level, a first tall gate electrode (130) forming a common gate for the first complementary transistor pair and arranged along a horizontal first gate track, and a first short gate electrode (140) forming a gate for the first pass transistor and arranged along a second gate track, a second tall gate electrode (230) forming a common gate for the second complementary transistor pair and arranged along the second gate track, a second short gate electrode (240) forming a gate for the second pass transistor and arranged along the first gate track, first and second contact arrangements (150, 250) forming a common drain contact for the transistors of the first set and the second set, respectively, and first and second cross-couple contacts (170, 270) extending horizontally between and interconnecting the first tall gate electrode and the second contact arrangement, and the second tall gate electrode and the first contact arrangement, respectively.