Stacked SRAM Cell Layout With Vertical NFET-PFET Layers
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Solution Overview
Problem
Current SRAM devices with 6-transistor cells face challenges in optimizing transistor placement and layout for improved density and reduced leakage current, particularly in integrating nanosheet field-effect transistors, which affects the packing density and power consumption.
Innovation Solution
The implementation of a stacked layer memory structure where one layer comprises NFETs and another layer comprises PFETs, with transistors stacked vertically, allowing for a single FET pitch-defined cell width, enabling improved density and reduced bit line capacitance by integrating SRAM cells with logic cells without interface gaps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar field-effect transistors are used in SRAM bitcells, then the device structure is simple and easy to manufacture, but the packing density is low and leakage current is high
Solution Approach 1:
The patent transitions from planar (2D) field-effect transistors to FinFET (3D) structures, where the gate electrode wraps around the fin channel in a tri-gate configuration. This dimensional change increases the effective channel width and gate control area without increasing the footprint area, thereby improving packing density while maintaining manufacturability through established semiconductor fabrication processes
2Device complexity
If planar field-effect transistors are used in SRAM bitcells, then the device structure is simple, but the leakage current is high
Solution Approach 1:
The FinFET structure provides enhanced gate control over the channel through the wrapped gate electrode, which suppresses short-channel effects and reduces off-state leakage current. The vertical fin structure allows the gate to control carriers from three sides, improving threshold voltage control and reducing leakage compared to planar devices
Solution Approach 2:
The patent employs selective epitaxial growth to create composite semiconductor structures with different conductivity types (n-type and p-type regions) integrated in a three-dimensional arrangement. This composite structure enables complementary FinFET configurations that reduce leakage current through improved carrier control and offset gate configurations
3Quantity of substance
If stacked layer memory structure is implemented, then the packing density is improved and bit line length is reduced, but the device structure becomes more complex
Solution Approach 1:
The patent implements a stacked layer architecture where complementary FinFETs (n-type and p-type) are positioned in different vertical layers. This 3D stacking reduces the lateral footprint of each SRAM bitcell while maintaining full functionality, improving packing density without requiring overly complex interconnect structures since vertical proximity enables direct coupling
4Ease of operation
If stacked layer memory structure is implemented, then the bit line length and capacitance are reduced by 40-50%, but the manufacturing process becomes more complex
Solution Approach 1:
The patent segments the SRAM bitcell into multiple functional layers with n-type FinFETs in one layer and p-type FinFETs in another layer. This segmentation allows independent optimization of each transistor type and simplifies the formation of complementary structures, reducing manufacturing complexity despite the 3D architecture
Solution Approach 2:
The patent employs preliminary epitaxial growth to form the three-dimensional FinFET structures and source/drain regions before gate patterning. This preliminary formation of vertical structures simplifies subsequent processing steps and enables self-aligned fabrication, reducing overall manufacturing complexity despite the advanced 3D architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances memory cell density, reduces bit line capacitance by 40-50%, allows for embedded memory arrays, and facilitates low-resistance wiring and connections, while maintaining uniformity and complexity on the NFET layer.
Implementation Method 1
a gate electrode that wraps around the fin. During operation, a channel for carrier flow is formed in the fin between the source/drain regions. In comparison with planar field-effect transistors, the arrangement between the gate structure and fin improves control over the channel
Implementation Method 2
The source/drain regions of a nanosheet field-effect transistor may be epitaxially grown from the side surfaces of the nanosheet channel layers in spaces between adjacent layer stacks
Data Source
AI summary
A stacked layer memory for a SRAM includes a first layer of the SRAM, including multiple transistors of a first type, and includes a second layer of the SRAM, having multiple transistors of a second type. The first and second layers are different layers stacked vertically. A width of individual SRAM cells of the stacked layer memory is defined at least by a pitch of a single transistor of the transistors of the first type and the transistors of the second type. A method for forming the stacked layer memory for the SRAM includes forming the first layer and the second layer. The first and second layers are different layers and are formed to be stacked vertically. A width of individual SRAM cells of the stacked layer memory is defined at least by a pitch of a single transistor of the transistors of the first and second types.