Stacked SRAM Cell Interconnect Layout for Lower Via Capacitance
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Solution Overview
Problem
Stacked SRAM cells face challenges in reducing cell area and improving performance due to high via capacitances and limited word line and bit line widths, making it difficult to scale down the cell area further.
Innovation Solution
A stacked SRAM cell design with a compact interconnect structure, where power rails are arranged above transistor structures and bit lines are placed below, allowing for dual-side BEOL processing to reduce via lengths and increase line widths, thereby lowering capacitance and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If transistors are stacked in multiple tiers to reduce cell area, then cell area is reduced, but via capacitances increase due to longer vias
Solution Approach 1:
The patent applies dual-side BEOL processing to connect transistor tiers from both top and bottom sides, effectively adding a dimensional approach to via routing. This allows vias to be formed from both upward and downward directions, reducing the effective via length and associated capacitance while maintaining the stacked configuration for area reduction.
Solution Approach 2:
The interconnect structure is segmented into multiple via segments formed from different sides. Instead of single long vias, the connection path is divided into shorter segments that can be independently optimized, reducing the total via capacitance while maintaining electrical connectivity across stacked tiers.
2Area of stationary object
If transistors are stacked in multiple tiers to reduce cell area, then cell area is reduced, but word line and bit line widths are limited
Solution Approach 1:
By implementing dual-side BEOL processing, the patent utilizes both top and bottom sides of the stacked structure for interconnect routing. This dimensional approach allows word lines and bit lines to be wider since they can be distributed across multiple levels and sides, increasing effective conduction area without expanding the planar cell footprint.
Solution Approach 2:
The patent merges interconnect paths from both top and bottom sides to form comprehensive word line and bit line networks. By combining routing resources from dual sides, the effective line widths are increased through parallel conduction paths, improving current carrying capacity while maintaining compact cell area.
3Object-generated harmful factors
If via lengths are reduced to lower via capacitances, then via capacitances are reduced, but cell area reduction is limited
Solution Approach 1:
The patent resolves this contradiction by utilizing dual-side processing to form vias from both top and bottom directions. This allows the horizontal projection of vias to be shorter (reducing capacitance) while the vertical stacking maintains area efficiency. The via length is reduced in the lateral direction while the stacked architecture preserves the area benefits.
Data Source
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Figure 2(a)~2(b)
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AI summary
The present disclosure relates to static random access memory (SRAM). In particular, the disclosure provides a stacked SRAM cell, and a method for fabricating the stacked SRAM cell. The stacked SRAM cell comprises two first transistor structures and two second transistor structures, which form a pair of cross-coupled inverters, an comprises one or two pass gate (PG) transistor structures. Further, the stacked SRAM cell comprises a first power rail and/or a second power rail arranged above the transistor structures, wherein the first power rail is connected by respective first vias to the first transistor structures from above, and/or the second power rail is connected by respective second vias to the second transistor structures from above. The SRAM cell also comprises one or two bit lines arranged below the PG transistor structures. Each bit line is connected by a respective third via to one PG transistor structure from below.