3D Stacked Storage Chip Layout for Area Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional storage devices require a large space due to the non-overlapping structure areas of various components, which hinders the minimization of device size.
Innovation Solution
A storage device comprising a first chip with a storage array and a second chip stacked on top, where the second chip includes local and word line decoders that are electrically connected to the storage array, forming non-overlapping blocks within a top view projection area, allowing for reduced occupied space by optimizing the layout and connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the structure areas of storage arrays, local bit line decoders, word line decoders, and peripheral circuits are arranged non-overlapping in conventional storage devices, then the electrical connections between components can be simplified, but the occupied space increases significantly
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked architecture. The first chip contains storage arrays while the second chip contains decoders, stacking them vertically along the third direction. This dimensional change allows decoder blocks to overlap with storage block projections in the top view, dramatically reducing the occupied area while maintaining electrical connection simplicity through vertical interconnections.
Solution Approach 2:
The storage device is segmented into two separate chips: a first chip for storage arrays and a second chip for decoders. Each chip is further divided into multiple blocks (storage blocks, local bit line decoder blocks, word line decoder blocks) that can be independently designed and optimized. This segmentation enables the overlapping projection arrangement while simplifying electrical connections within each chip layer.
2Area of stationary object
If decoder blocks are arranged to overlap with storage block projections in the top view, then the occupied area is reduced, but the electrical connections become more complex
Solution Approach 1:
By moving the decoder blocks to a different vertical layer (second chip stacked on the first chip), the patent eliminates the need for complex lateral electrical connections. The overlapping projection in the top view is achieved without increasing connection complexity because connections are made vertically through the stack using inter-layer vias and bonding pads, simplifying the routing architecture.
Solution Approach 2:
The patent introduces intermediary connection structures including bonding pads on both chips and inter-layer vias that facilitate electrical connections between the storage arrays on the first chip and the decoders on the second chip. These intermediaries manage the complexity of connections between overlapping blocks by providing standardized connection interfaces at each layer.
3Area of stationary object
If multiple decoder blocks are arranged within the projection area of a storage block, then the device size is minimized, but the layout design becomes more difficult
Solution Approach 1:
The decoders are segmented into multiple independent decoder blocks (local bit line decoder blocks and word line decoder blocks) that can be separately designed and optimized. Each block has a defined projection area that overlaps with the storage block projection, allowing systematic arrangement and simplifying the layout design process while minimizing device size.
Solution Approach 2:
The decoder blocks are designed with universal interfaces and standardized configurations that can be replicated and arranged in different patterns within the storage block projection area. This multi-functionality approach allows the same decoder block design to serve multiple storage blocks, simplifying layout design while achieving compact integration.
Data Source
AI summary
A storage device and a manufacturing method thereof are provided. The storage device includes a first chip and a second chip. The second chip is stacked on the first chip in a third direction. The first chip includes a storage array, and the storage array includes at least one storage block. An occupied area after the first chip and the second chip are stacked can be reduced by constructing a first local bit line decoder block, a second local bit line decoder block, a first word line decoder block, and a second local bit line decoder block in a top view projection area, thereby reducing plane occupied space of the storage device. This is beneficial for minimizing the size of the storage device.