3D Stacked Storage Memory Layout for Faster Direct Control
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Solution Overview
Problem
Conventional storage devices with non-volatile memory, buffer memory, and memory controller disposed on the same plane occupy a large area, reducing integration efficiency, increasing size, and slowing operating speed due to the need for interpreting command signals.
Innovation Solution
The non-volatile memory, buffer memory, and memory controller are integrated into a single stacked chip structure, minimizing connection lengths and eliminating the need for command signal interpretation by direct control signal application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If non-volatile memory, buffer memory, and memory controller are disposed on the same plane, then device complexity is reduced, but area occupied increases and operating speed decreases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked configuration. Multiple memory layers and controller are vertically stacked, allowing components to occupy different height levels rather than spreading out horizontally. This dimensional change resolves the contradiction by maintaining low structural complexity while dramatically reducing the footprint area.
2Device complexity
If non-volatile memory, buffer memory, and memory controller are disposed on the same plane, then device complexity is reduced, but operating speed decreases due to command signal interpretation
Solution Approach 1:
The patent merges the memory storage function and control function into a single integrated stacked chip structure. The controller is directly connected to memory layers through vertical vias, eliminating the need for separate command signal interpretation processes. This merging resolves the contradiction by improving operating speed through direct control while maintaining integrated design simplicity.
3Area of stationary object
If components are integrated into a single stacked chip, then area occupied is reduced and operating speed is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the storage device into distinct functional layers (non-volatile memory layer, buffer memory layer, controller layer) that can be manufactured separately and then stacked. Each layer can be optimized and manufactured independently using standard semiconductor processes, then assembled through wafer bonding or chip stacking techniques. This segmentation resolves the contradiction by reducing device size through integration while managing manufacturing complexity through modular fabrication.
4Speed
If components are integrated into a single stacked chip, then operating speed is enhanced by direct connection, but connection structure complexity increases
Solution Approach 1:
The patent uses vertical vias and through-silicon vias (TSVs) to create direct three-dimensional interconnections between stacked layers. Instead of requiring complex two-dimensional routing on a single plane, signals travel vertically through dedicated conductive paths. This dimensional approach resolves the contradiction by achieving high-speed direct connections while managing connection complexity through standardized vertical interconnect structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the size of the storage device and enhances operating speed by providing a direct connection path with reduced power consumption and signal delay.
Implementation Method 1
a first metal pad disposed above the first cell area and a second metal pad disposed above the peripheral circuit are bonded to each other in a direction perpendicular to an upper surface of the first semiconductor substrate
Implementation Method 2
A connection structure penetrates through the second semiconductor substrate and is electrically connected to the third semiconductor substrate
Data Source
AI summary
A storage device includes a first semiconductor structure having a first cell area, with memory cells disposed on a first semiconductor substrate, and a first metal pad disposed above the first cell area. A second semiconductor structure has a peripheral circuit area on a second semiconductor substrate and on which peripheral circuits are disposed, a second cell area including a plurality of second memory cells, and a second metal pad bonded to the first metal pad. A third semiconductor structure includes a memory controller disposed on a third semiconductor substrate and connected to a third metal pad through a connection via penetrating through the third semiconductor substrate. A connection structure penetrates through the second semiconductor substrate and connects the memory controller to the second semiconductor structure. The memory controller controls the first and second cell areas based on a signal applied from a host through the third metal pad.