Stacked Storage Array Latency Control by Die-Level Access Characteristics
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Solution Overview
Problem
Conventional systems assume a worst-case access latency for storage array extensions on stacked dies, leading to reduced overall performance by delaying data access even when faster storage circuits are available.
Innovation Solution
Implement control logic to set response latency based on the specific characteristics of each storage circuit, such as stack position, material, circuit technology, or layout type, allowing faster circuits to respond quicker than slower ones.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a worst-case access latency is assumed for storage array extensions on stacked dies, then access consistency is simplified, but overall system performance deteriorates due to unnecessary delays
Solution Approach 1:
The patent implements dynamic latency adjustment where the access latency is no longer fixed to a worst-case value but varies based on the actual characteristics of the storage circuit being accessed. The system determines and applies appropriate latency values corresponding to different storage circuit types (e.g., faster latency for lower-tier circuits, slower latency for higher-tier circuits), allowing the system to adapt latency dynamically rather than using a static conservative estimate.
2Quantity of substance
If storage circuits are placed on higher positioned dies in the stack, then storage capacity is increased, but access latency increases due to greater vertical distance from the processor
Solution Approach 1:
The patent applies different latency characteristics to different parts of the storage array based on their physical location and circuit type. Storage circuits on lower positioned dies (closer to the processor) are assigned shorter latency values, while storage circuits on higher positioned dies (further from the processor) are assigned longer latency values. This localized differentiation allows the system to account for actual access distances rather than using a uniform latency estimate.
3Device complexity
If a uniform worst-case latency is applied to all storage circuits, then control logic complexity is reduced, but processing time increases due to unnecessary waiting
Solution Approach 1:
The patent changes the latency parameter from a fixed worst-case value to a variable value that depends on the specific storage circuit characteristics. The control logic determines which storage circuit is being accessed and applies the corresponding latency parameter (e.g., first latency for faster circuits, second latency for slower circuits). This parameter differentiation allows the system to optimize processing time without requiring overly complex control mechanisms.
Data Source
AI summary
Variable access latency with storage array extensions on stacked dies. In one or more implementations, a system includes a storage array having a plurality of storage circuits implemented on different dies in a stack of dies, and control logic operable to receive responses from the storage circuits in reply to storage circuit requests forwarded through the stack of dies and output the responses according to a respective latency that delays each response based on a characteristic of a corresponding storage circuit that provides the response. In at least one implementation, a device includes a control logic that outputs responses from a stacked storage array having a plurality of storage circuits according to a respective latency that delays each response based on a characteristic of a corresponding storage circuit that provides the response.